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# ====================================================================## hal_openrisc_orpsoc.cdl## OpenRISC Reference Platform (ORP) HAL package configuration data## ====================================================================## ####ECOSGPLCOPYRIGHTBEGIN###### -------------------------------------------## This file is part of eCos, the Embedded Configurable Operating System.## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.#### eCos is free software; you can redistribute it and/or modify it under## the terms of the GNU General Public License as published by the Free## Software Foundation; either version 2 or (at your option) any later## version.#### eCos is distributed in the hope that it will be useful, but WITHOUT## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License## for more details.#### You should have received a copy of the GNU General Public License## along with eCos; if not, write to the Free Software Foundation, Inc.,## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.#### As a special exception, if other files instantiate templates or use## macros or inline functions from this file, or you compile this file## and link it with other works to produce a work based on this file,## this file does not by itself cause the resulting work to be covered by## the GNU General Public License. However the source code for this file## must still be made available in accordance with section (3) of the GNU## General Public License v2.#### This exception does not invalidate any other reasons why a work based## on this file might be covered by the GNU General Public License.## -------------------------------------------## ####ECOSGPLCOPYRIGHTEND##### ====================================================================######DESCRIPTIONBEGIN###### Author(s): sfurman# Contributors:# Date: 2003-01-20######DESCRIPTIONEND###### ====================================================================cdl_package CYGPKG_HAL_OPENRISC_ORPSOC {display "OpenRISC System-on-Chip"parent CYGPKG_HAL_OPENRISCinclude_dir cyg/halhardwaredescription "The ORPSoC HAL package should be used when targetting theOpenRISC Reference Platform."compile hal_diag.c hal_aux.cimplements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORTimplements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORTimplements CYGINT_HAL_DEBUG_GDB_STUBSimplements CYGINT_HAL_DEBUG_GDB_STUBS_BREAKdefine_proc {puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_openrisc.h>"puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_openrisc_orpsoc.h>"}cdl_component CYG_HAL_STARTUP {display "Startup type"flavor datalegal_values {"RAM" "ROM" "JTAG"}default_value {"JTAG"}no_definedefine -file system.h CYG_HAL_STARTUPdescription "Selects whether code initially runs from ROM or RAM. In the case of ROM startup,it's possible for the code to be copied into RAM and executed there."}cdl_component CYGHWR_MEMORY_LAYOUT {display "Memory layout"flavor datano_definecalculated { CYG_HAL_STARTUP == "ROM" ? "openrisc_orpsoc_rom" : \"openrisc_orpsoc_ram" }cdl_option CYGHWR_MEMORY_LAYOUT_LDI {display "Memory layout linker script fragment"flavor datano_definedefine -file system.h CYGHWR_MEMORY_LAYOUT_LDIcalculated { CYG_HAL_STARTUP == "ROM" ? "<pkgconf/mlt_openrisc_orpsoc_rom.ldi>" : \"<pkgconf/mlt_openrisc_orpsoc_ram.ldi>" }}cdl_option CYGHWR_MEMORY_LAYOUT_H {display "Memory layout header file"flavor datano_definedefine -file system.h CYGHWR_MEMORY_LAYOUT_Hcalculated { CYG_HAL_STARTUP == "ROM" ? "<pkgconf/mlt_openrisc_orpsoc_rom.h>" : \"<pkgconf/mlt_openrisc_orpsoc_ram.h>" }}}# Real-time clock/counter specificscdl_component CYGNUM_HAL_RTC_CONSTANTS {display "Real-time clock constants."flavor nonecdl_option CYGNUM_HAL_RTC_NUMERATOR {display "Real-time clock numerator"flavor datadefault_value 1000000000}cdl_option CYGNUM_HAL_RTC_DENOMINATOR {display "Real-time clock denominator"flavor datadefault_value 100}cdl_option CYGNUM_HAL_RTC_PERIOD {display "Real-time clock period"flavor datadefault_value {CYGHWR_HAL_OPENRISC_CPU_FREQ * 1000000 / CYGNUM_HAL_RTC_DENOMINATOR}description "The tick timer facility is usedto drive the eCos kernel RTC. The count registerincrements at the CPU clock speed. By default, 100 Hz"}}cdl_component CYGBLD_GLOBAL_OPTIONS {display "Global build options"flavor nonedescription "Global build options including control overcompiler flags, linker flags and choice of toolchain."parent CYGPKG_NONEcdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {display "Global command prefix"flavor datano_definedefault_value { "or32-elf" }description "This option specifies the command prefix used wheninvoking the build tools."}cdl_option CYGBLD_GLOBAL_CFLAGS {display "Global compiler flags"flavor datano_definedefault_value { CYGBLD_GLOBAL_WARNFLAGS ."-g -O2 -fno-omit-frame-pointer -fno-rtti -fno-exceptions " .(CYGHWR_MUL_IMPLEMENTED ? "-mhard-mul " : "-msoft-mul ") .(CYGHWR_DIV_IMPLEMENTED ? "-mhard-div " : "-msoft-div ") .(CYGHWR_FPU_IMPLEMENTED ? "-mhard-float " : "-msoft-float ") .(CYGHWR_BRANCH_SLOT_IMPLEMENTED ? "" : "-mno-delay " ) }description "This option controls the global compiler flags whichare used to compile all packages bydefault. Individual packages may defineoptions which override these global flags."}cdl_option CYGBLD_GLOBAL_LDFLAGS {display "Global linker flags"flavor datano_definedefault_value { "-g -O2 -nostdlib -Wl,--gc-sections -Wl,-static " .(CYGHWR_MUL_IMPLEMENTED ? "-mhard-mul " : "-msoft-mul ") .(CYGHWR_DIV_IMPLEMENTED ? "-mhard-div " : "-msoft-div ") .(CYGHWR_FPU_IMPLEMENTED ? "-mhard-float " : "-msoft-float ") .(CYGHWR_BRANCH_SLOT_IMPLEMENTED ? "" : "-mno-delay " ) }description "This option controls the global linker flags. Individualpackages may define options which override these global flags."}}cdl_option CYGBLD_BUILD_GDB_STUBS {display "Build GDB stub ROM image"default_value 0parent CYGBLD_GLOBAL_OPTIONSrequires { CYG_HAL_STARTUP == "ROM" }requires CYGSEM_HAL_ROM_MONITORrequires CYGBLD_BUILD_COMMON_GDB_STUBSrequires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBSrequires ! CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORTrequires ! CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORTrequires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXTrequires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUMno_definedescription "This option enables the building of the GDB stubs for theboard. The common HAL controls takes care of most of thebuild process, but the final conversion from ELF image tobinary data is handled by the platform CDL, allowingrelocation of the data if necessary."make -priority 320 {<PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img$(OBJCOPY) -O binary $< $@}}cdl_option CYGNUM_HAL_BREAKPOINT_LIST_SIZE {display "Number of breakpoints supported by the HAL."flavor datadefault_value 25description "This option determines the number of breakpoints supported by the HAL."}cdl_option CYGSEM_HAL_USE_ROM_MONITOR {display "Work with a ROM monitor"flavor booldefault_value { CYG_HAL_STARTUP == "RAM" ? 1 : 0 }parent CYGPKG_HAL_ROM_MONITORrequires { CYG_HAL_STARTUP == "RAM" }description "Allow coexistence with ROM monitor (CygMon or GDB stubs) byonly initializing interrupt vectors on startup, thus leavingexception handling to the ROM monitor."}cdl_option CYGSEM_HAL_ROM_MONITOR {display "Behave as a ROM monitor"flavor booldefault_value 0parent CYGPKG_HAL_ROM_MONITORrequires { CYG_HAL_STARTUP == "ROM" }description "Enable this option if this program is to be used as a ROM monitor,i.e. applications will be loaded into RAM on the board, and thisROM monitor may process exceptions or interrupts generated from theapplication. This enables features such as utilizing a separateinterrupt stack when exceptions are generated."}cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {display "Redboot HAL options"flavor noneno_defineparent CYGPKG_REDBOOTactive_if CYGPKG_REDBOOTdescription "This option lists the target's requirements for a valid Redbootconfiguration."cdl_option CYGBLD_BUILD_REDBOOT_BIN {display "Build Redboot ROM binary image"active_if CYGBLD_BUILD_REDBOOTdefault_value 1no_definedescription "This option enables the conversion of the Redboot ELFimage to a binary image suitable for ROM programming."compile -library=libextras.amake -priority 325 {<PREFIX>/bin/redboot.srec : <PREFIX>/bin/redboot.elf$(OBJCOPY) --strip-all $< $(@:.srec=.img)$(OBJCOPY) -O srec $< $@}}}cdl_option CYGHWR_HAL_OPENRISC_CPU_FREQ {display "CPU frequency"flavor datalegal_values 0 to 1000000default_value 50description "This option contains the frequency of the CPU in MegaHertz.Choose the frequency to match the processor you have. Thismay affect thing like serial device, interval clock andmemory access speed settings."}cdl_option CYGHWR_MUL_IMPLEMENTED {display "Hardware multiplier implemented"flavor booldefault_value 1description "Select this option only if hardware multiplier isimplemented."}cdl_option CYGHWR_DIV_IMPLEMENTED {display "Hardware divisor implemented"flavor booldefault_value 1description "Select this option only if hardware division isimplemented."}cdl_option CYGHWR_FPU_IMPLEMENTED {display "Hardware FPU implemented"flavor booldefault_value 0description "Select this option only if FPU is implemented."}cdl_option CYGHWR_BRANCH_SLOT_IMPLEMENTED {display "Branch slot implemented"flavor booldefault_value 1description "Select this option if your implementation of OpenRISChas branch slot."}cdl_component CYGHWR_ICACHE_IMPLEMENTED {display "Instruction cache implemented"flavor booldefault_value 1description "Select this option only if instruction cache isimplemented."cdl_option CYGHWR_ICACHE_SIZE {display "Size of instruction cache"flavor datalegal_values 0x1000 0x2000 0x4000 0x8000default_value 0x2000description "Size of the instruction cache. Default is 8kB."}}cdl_component CYGHWR_DCACHE_IMPLEMENTED {display "Data cache implemented"flavor booldefault_value 1description "Select this option only if data cache isimplemented."cdl_option CYGHWR_DCACHE_SIZE {display "Size of data cache"active_if CYGHWR_DCACHE_IMPLEMENTEDflavor datalegal_values 0x200 0x1000 0x2000 0x4000 0x8000default_value 0x1000description "Size of the data cache. Default is 4kB."}cdl_option CYGHWR_DCACHE_MODE {display "DATA cache mode"flavor datalegal_values { "WRITETHROUGH" "WRITEBACK" }default_value { "WRITETHROUGH" }description "Speficy synthesized cache."}}cdl_option CYGHWR_RAM_SIZE {display "Size of RAM memory"flavor datadefault_value 0x2000000description "Size of RAM memory. This value is used to generate linker script.Default is 32MB."}cdl_option CYGHWR_ROM_SIZE {display "Size of ROM memory"flavor datadefault_value 0x40000description "Size of ROM memory. This value is used to generate linker script.Default is 256kB."}cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {display "Diagnostic serial port baud rate"flavor datalegal_values 9600 19200 38400 57600 115200 230400 460800 921600default_value 115200description "This option selects the baud rate used for the diagnostic console.Note: this should match the value chosen for the GDB port if thediagnostic and GDB port are the same.Note: very high baud rates are useful during simulation."}cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {display "GDB serial port baud rate"flavor datalegal_values 9600 19200 38400 57600 115200 230400 460800 921600default_value 115200description "This option controls the baud rate used for the GDB connection.Note: very high baud rates are useful during simulation."}cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {display "Number of communication channels on the board"flavor datadefault_value 1}cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {display "Debug serial port"active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLEflavor datalegal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1default_value 0description "The ORP platform has at least one serial port, but it can potentially have several.This option chooses which port will be used to connect to a hostrunning GDB."}cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {display "Diagnostic serial port"active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLEflavor datalegal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1default_value 0description "The ORP platform has at least one serial port, but it can potentially have several.This option chooses which port will be used for diagnostic output."}define_proc {puts $cdl_header "#define CYGHWR_HAL_VSR_TABLE 0"puts $cdl_header "#define CYGHWR_HAL_VIRTUAL_VECTOR_TABLE 0xF00"}}# EOF hal_openrisc_orpsoc.cdl
