Main Page   Modules   Related Pages  

External interrupt 0

Features
External interrupt 0 is physically mapped on the line 0 (bit 0) of port A.

Its associated interrupt flag resides into the IO File register GIFR (General Interrupt Flags Register):

pavr_hwres_iof_perif_int0_01.gif

External interrupt 0 is enabled/disabled by setting/clearing bit 6 in GIMSK (General Interrupt Mask) register:

pavr_hwres_iof_perif_int0_02.gif

If enabled, it can trigger an interrupt on high-to-low transition, low-to-high transition, or on a low level of the interrupt 0 input. This behavior is defined by 2 bits in the MCUCR (Microcontroller Control) register:

pavr_hwres_iof_perif_int0_03.gif


Generated on Sat Jul 3 08:13:38 2004 for Pipelined AVR microcontroller by doxygen1.2.12 written by Dimitri van Heesch, © 1997-2001