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Some final thoughts

Instead of conclusion...
It's relatively easy to design a fast 8 bit controller. All that has to be done is to follow the path well known from the big brothers, the 32 bit controllers. The short story is: analyze what "typical programs" mean, imagine a simple and fast instruction set, and implement it into a deep pipeline (by the way, for this topics, I recommend you "Computer architecture - a quantitative approach", by J. Hennessy and D. Patterson).

Then, why are the 8 bit controllers currently on the market so slow? The instruction set, CPI, max frequency for current 8 bit ucs are bad. In fact, they are so bad, that we must consider other factors than pure uc design to explain that. My guess is that market issues distructively interfere here. How is that, this could be another project's goal...
Updating this documentation... soon, a better version will be available
As a result of constructive criticism I received, I'll modify the structure of this documentation in order to make it easier to digest. I'll include detailed but concise information about AVR architecture, and organize the whole stuff on a top-down framework.
By the way, in this summer (2004) I plan to burn pAVR into an FPGA and complete the testing.



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