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Sources
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Sources
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The source package contains the following files, in the compiling order:
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Test sources
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The test sources in this package implement all the tests presented above.
The test source package contains the following files:
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Conventions used when writting the VHDL sources
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The terminology used reflects the data flow.
For example, `pavr_s4_s6_rfwr_addr1' is assigned in s3 (by the instruction decoder), shifts into `pavr_s5_s6_rfwr_addr1', that finally shifts into `pavr_s6_rfwr_addr1' (terminal register). Only this one carries information actually used by hardware resource managers. This particualr one signalizes an access request to the Register File write port manager.
Process splitting strategy:
- requests to hardware resources are managed by dedicated processes, one VHDL process per hardware resource.
- a main asynchronous process (instruction decoder) computes values that initialize the pipeline in s3.
- a main synchronous process assings new values to pipeline registers.
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Todo:
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Replace `next_...' signals family with a (pretty wide) state decoder.
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Licensing
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Please read the licensing terms.
Generated on Sat Jul 3 08:13:38 2004 for Pipelined AVR microcontroller by
1.2.12 written by Dimitri van Heesch,
© 1997-2001