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[/] [powersupplysequencer/] [vhdl/] [msi/] [PowerSequencer/] [PowerSequencer_tb.vhd] - Rev 2

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-- Test bed for power sequencer slice
 
-- (c) 2009.. Gerhard Hoffmann  opencores@hoffmann-hochfrequenz.de
-- Published under BSD license
-- V1.0   first published version
--
-- 3 sequencer slices and 3 simulated power supplies are connected together.
--
-- A power-up --> normal operation --> power-down is performed.
--
-- Then there is another power-up --> normal operation cycle that is
-- aborted when the middle power supply decides to run too hot at t = 70 msec.
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
 
 
 
entity PowerSequencer_tb is end entity PowerSequencer_tb;
 
 
architecture tb of PowerSequencer_tb is
 
	constant ticks:             integer := 30; -- Power supplies must be up within 30 10KHz clock cycles
 
	signal clk, rst:            std_logic;
 
	signal ps1_defective:       boolean;
	signal ps2_defective:       boolean;
	signal ps3_defective:       boolean;
 
	signal power_up:            std_logic;                        -- the mains switch
	signal all_power_good:      std_logic;                        -- the green power lamp
 
	signal ena_stage2, ena_stage3:                    std_logic;  -- mains switch for the slaves
	signal fail_chain123, fail_chain23, fail_chain3:  std_logic;  -- fail outputs of the groups
	signal pu_chain123, pu_chain23, pu_chain3:        std_logic;  -- power up status of the groups
	signal vout1, vout2, vout3:                       real;       -- output voltages of the supplies
 
	signal ena_supply1:		       std_logic;
	signal supply1good:			     std_logic;
 
	signal ena_supply2:		       std_logic;
	signal supply2good:			     std_logic;
 
	signal ena_supply3:		       std_logic;
	signal supply3good:			     std_logic;
 
begin
 
 
uck: entity work.clk_rst    -- standard clock and reset source
 
  generic map(        
    clock_frequency   => 10.0e3,   -- 10 KHz
    min_resetwidth    => 5 ms,
    verbose           => false         
  )
 
  port map(        
    clk               => clk,
    rst               => rst
  ); 
 
 
power_up            <= '0', 
                       '1' after 10 ms, 
                       '0' after 40 ms, 
                       '1' after 70 ms, 
                       '0' after 100 ms;
 
ps1_defective       <= false;
ps2_defective       <= false, true after 90 ms;
ps3_defective       <= false;
 
all_power_good      <= power_up and pu_chain123 and (not fail_chain123);
 
uPS1: entity work.PowerSequencer
generic map (
	ticks             => ticks,
	last_in_chain     => false
)
port map (
  clk               => clk,
  rst               => rst,
 
  ena_chain_async   => power_up,
  fail_chain_out    => fail_chain123,
  pu_chain_out      => pu_chain123,
 
  ena_next          => ena_stage2,
  fail_chain_in     => fail_chain23,
  pu_chain_ini      => pu_chain23,
 
  supply_enai       => ena_supply1,
  supply_good_async => supply1good
);
 
 
uPS2: entity work.PowerSequencer
generic map (
  ticks             => ticks,
  last_in_chain     => false
 
port map (
  clk               => clk,
  rst               => rst,
 
  ena_chain_async   => ena_stage2,
  fail_chain_out    => fail_chain23,
  pu_chain_out      => pu_chain23,
 
  ena_next          => ena_stage3,
  fail_chain_in     => fail_chain3,
  pu_chain_in       => pu_chain3,
 
  supply_ena        => ena_supply2,
  supply_good_async => supply2good
);
 
 
uPS3: entity work.PowerSequencer
generic map (
  ticks             => ticks,
  last_in_chain     => true
)
port map (
  clk               => clk,
  rst               => rst,
 
  ena_chain_async   => ena_stage3,
  fail_chain_out    => fail_chain3,
  pu_chain_out      => pu_chain3,
 
  ena_next          => open,
  fail_chain_in     => '0',  
  pu_chain_in       => '0',   
 
  supply_ena        => ena_supply3,
  supply_good_async => supply3good
);
 
-------------------------------------------------------------------------
 
 
usup1: entity work.powersupply
generic map (
  voltage           => 1.8,    -- volts
  risetime          => 2.0e-3  -- seconds
)
port map (
  defective         => ps1_defective,
  ena               => ena_supply1,
  pgood             => supply1good,
  vout              => vout1
);
 
 
usup2: entity work.powersupply
generic map (
  voltage           => 3.3,
  risetime          => 2.0e-3
)
port map(
  defective         => ps2_defective,
  ena               => ena_supply2,
  pgood             => supply2good,
  vout              => vout2
);
 
 
usup3:entity work.powersupply
generic map(
  voltage           => 1.1,
  risetime          => 2.0e-3
)
port map(
  defective         => ps3_defective,
  ena               => ena_supply3,
  pgood             => supply3good,
  vout              => vout3
);
 
end architecture tb;
 
 

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