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[/] [powersupplysequencer/] [vhdl/] [tb/] [PowerSupply/] [PowerSupply.vhd] - Rev 2

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-- simple power supply model for testbeds.
-- here we are not interested in line regulation. We just want to see
-- the reaction to the enable signal, the rough behaviour of the output
-- voltage and that it asserts powergood when the output voltage approaches
-- the intended value. And it breaks on command.
 
-- (c) 2009.. Gerhard Hoffmann  opencores@hoffmann-hochfrequenz.de
-- published under BSD conditions.
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use ieee.math_real.all;
 
 
 
entity PowerSupply is
  generic (
    voltage:    real := 3.3;
    risetime:   real := 1.0e-3    -- one millisecond
  );
 
  port (
    defective: in  boolean;
    ena:       in  std_logic;
    pgood:     out std_logic;
    vout:      out real
  );
end entity PowerSupply;
 
 
 
architecture behave of PowerSupply is
 
  signal cur_voltage:  real := 0.0;
  signal voltage_goal: real := 0.0;
 
 
  function bool2sl (b: boolean) return std_logic is
  begin
    if b  then return '1'; else return '0'; end if;
  end function bool2sl;
 
 
 
begin
 
u_regulate: process is
begin
 
  if ena = '1' 
  then 
    voltage_goal <= voltage; 
  else 
    voltage_goal <= 0.0; 
  end if;
 
  -- 1.0e-6 is for the 1 us timestep
  cur_voltage   <= cur_voltage + (voltage_goal - cur_voltage) * ((1.0e-6 * 3.0) / risetime);
 
  pgood <= bool2sl ( (cur_voltage > (0.95 * voltage)) and not defective);
  vout  <= cur_voltage;	
 
  wait for 1 us;
end process u_regulate;
 
 
end architecture behave;
 
 

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