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[/] [powersupplysequencer/] [vhdl/] [tb/] [PowerSupply/] [PowerSupply_tb.vhd] - Rev 2

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-- Testbed for the power supply
-- (c) 2009.. Gerhard Hoffmann  opencores@hoffmann-hochfrequenz.de
-- published under BSD conditions.
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
 
 
 
entity PowerSupply_tb is end entity PowerSupply_tb;
 
 
architecture tb of PowerSupply_tb is
 
  signal defective: boolean;
  signal ena:       std_logic;
  signal pgood:     std_logic;
  signal vout:      real;
 
begin
 
ena       <= '0', '1' after 10 ms, '0' after 20 ms, '1' after 35 ms;
defective <= false, true after 50 ms;
 
 
uut: entity work.PowerSupply
 
generic map (
  voltage    => 3.3,
  risetime   => 2.0e-3
)
 
port map (
  defective => defective,
  ena       => ena,
  pgood     => pgood,
  vout      => vout
);
 
end architecture tb;
 
 

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