URL
https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk
Subversion Repositories qaz_libs
[/] [qaz_libs/] [trunk/] [BFM/] [src/] [SPI/] [spi_if.sv] - Rev 48
Go to most recent revision | Compare with Previous | Blame | View Log
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2018 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
interface
spi_if();
import uvm_pkg::*;
`include "uvm_macros.svh"
import tb_spi_pkg::*;
// --------------------------------------------------------------------
logic sclk;
logic ss_n;
logic mosi;
logic miso;
// --------------------------------------------------------------------
time period = 40ns;
// --------------------------------------------------------------------
default clocking cb_rise @(posedge sclk);
inout ss_n;
output mosi;
input miso;
endclocking
// --------------------------------------------------------------------
clocking cb_fall @(negedge sclk);
inout ss_n;
output mosi;
input miso;
endclocking
// --------------------------------------------------------------------
task zero_cycle_delay;
##0;
endtask: zero_cycle_delay
// --------------------------------------------------------------------
endinterface
Go to most recent revision | Compare with Previous | Blame | View Log