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[/] [qaz_libs/] [trunk/] [BFM/] [src/] [tb/] [tb_base.sv] - Rev 46

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////

`timescale 1ps/1ps

import tb_clk_pkg::*;


module
  tb_base
  #(
    parameter PERIOD = 0,
    parameter ASSERT_TIME = 0
  )
  (
    output      clock,
    output reg  reset
  );

  // --------------------------------------------------------------------
  //
  task assert_reset
  (
    input time reset_assert
  );

    reset = 1;
    $display( "-#- %16.t | %m | reset asserted!", $time );

    #reset_assert;

    reset = 0;
    $display( "-#- %16.t | %m | reset deasserted!", $time );

endtask


  // --------------------------------------------------------------------
  //
  task timeout_stop
  (
    input time timeout
  );

    $display("-#- %16.t | %m | timeout_stop at %t", $time, timeout);

    fork
      #(timeout) $stop;
    join_none

endtask


  // --------------------------------------------------------------------
  //
  tb_clk_class tb_clk_c;
  tb_clk_if tb_clk_driver();
  assign clock = tb_clk_driver.clk;
  time reset_assert = (PERIOD * 5) + (PERIOD / 3);
  logic init_done = 0;

  initial
    begin

      reset = 1;

      tb_clk_c = new( tb_clk_driver );

      if( PERIOD != 0 )
        tb_clk_c.init_basic_clock( PERIOD );

      if( ASSERT_TIME != 0 )
        assert_reset( ASSERT_TIME );
      else if( reset_assert != 0 )
        assert_reset( reset_assert );

      init_done = 1;

    end
endmodule


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