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[/] [qaz_libs/] [trunk/] [PCIe/] [src/] [RIFFA/] [riffa_rx_to_axis.sv] - Rev 42
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//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module
riffa_rx_to_axis
#(
N // RIFFA bus width in bytes
)
(
axis_if axis_out,
riffa_chnl_if chnl_bus,
input rx_ready,
output rx_done,
output [30:0] rx_index,
output rx_last,
output [31:0] rx_len,
output [30:0] rx_off,
input clk,
input reset
);
// --------------------------------------------------------------------
//
wire rd_empty;
wire [(8*N)-1:0] rd_data;
wire rd_en = axis_out.tvalid & axis_out.tready;
riffa_chn_rx #(.N(N))
riffa_chn_rx_i(.*);
// --------------------------------------------------------------------
//
assign chnl_bus.rx_clk = clk;
assign chnl_bus.rx_reset = reset;
assign axis_out.tvalid = ~rd_empty;
assign axis_out.tdata = rd_data;
// --------------------------------------------------------------------
//
endmodule
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