Subversion Repositories qaz_libs

//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
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//// This source file may be used and distributed without         ////
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//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
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//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
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//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//////////////////////////////////////////////////////////////////////


interface
  amm_master_bfm_if
  #(
    A = 32, // address bus width
    N = 8   // data bus width in bytes
  )
  (
    amm_if amm_s,
    input reset,
    input clk
  );

        logic [(A-1):0]   address;
        logic             read;
        logic   [(8*N)-1:0] readdata;
        logic             write;
        logic   [(8*N)-1:0] writedata;
        logic   [N-1:0]     byteenable;
        logic             waitrequest;
        logic             arbiterlock;
        logic             readdatavalid;  
        logic   [6:0]       burstcount;
        logic               resetrequest;


  // --------------------------------------------------------------------
  //
  default clocking cb @(posedge clk);
    output address;
    output read;
    input  readdata;
    output write;
    output writedata;
    output byteenable;
    input  waitrequest;
    output arbiterlock;
    input  readdatavalid;
    output burstcount;
    output resetrequest;
    input   reset;
    input   clk;
  endclocking


  // --------------------------------------------------------------------
  //
  assign amm_s.address      = address;
  assign amm_s.read         = read;
  assign readdata           = amm_s.readdata;
  assign amm_s.write        = write;
  assign amm_s.writedata    = writedata;
  assign amm_s.byteenable   = byteenable;
  assign waitrequest        = amm_s.waitrequest;
  assign amm_s.arbiterlock  = arbiterlock;
  assign readdatavalid      = amm_s.readdatavalid;
  assign amm_s.burstcount   = burstcount;
  assign amm_s.resetrequest = resetrequest;


  // --------------------------------------------------------------------
  //
  function void
    amm_default;

    address       = 'bx;
    arbiterlock   = 0;
    burstcount    = 'bx;
    byteenable    = 'bx;
    read          = 0;
    resetrequest  = 0;
    write         = 0;
    writedata     = 'bx;

  endfunction: amm_default


  // --------------------------------------------------------------------
  //
  function void
    init;

    amm_default();

  endfunction: init


  // --------------------------------------------------------------------
  //
  task
    zero_cycle_delay;

    ##0;

  endtask: zero_cycle_delay
  
  
  // --------------------------------------------------------------------
  //
  initial
  begin
  
    init();
  
  end


// --------------------------------------------------------------------
//

endinterface