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[/] [qaz_libs/] [trunk/] [axi4_lib/] [sim/] [src/] [axi4_bfm/] [axi4_master_bfm_if.sv] - Rev 29

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////


interface
  axi4_master_bfm_if
  #(
    A = 32, // address bus width
    N = 8,  // data bus width in bytes
    I = 1   // ID width
  )
  (
    axi4_if axi4_s,
    input   aresetn,
    input   aclk
  );

  logic [(A-1):0]    araddr;
  logic [1:0]        arburst;
  logic [3:0]        arcache;
  logic [(I-1):0]    arid;
  logic [7:0]        arlen;
  logic              arlock;
  logic [2:0]        arprot;
  logic [3:0]        arqos;
  logic              arready;
  logic [3:0]        arregion;
  logic [2:0]        arsize;
  logic              arvalid;
  logic [(A-1):0]    awaddr;
  logic [1:0]        awburst;
  logic [3:0]        awcache;
  logic [(I-1):0]    awid;
  logic [7:0]        awlen;
  logic              awlock;
  logic [2:0]        awprot;
  logic [3:0]        awqos;
  logic              awready;
  logic [3:0]        awregion;
  logic [2:0]        awsize;
  logic              awvalid;
  logic [(I-1):0]    bid;
  logic              bready;
  logic [1:0]        bresp;
  logic              bvalid;
  logic [(8*N)-1:0]  rdata;
  logic [(I-1):0]    rid;
  logic              rlast;
  logic              rready;
  logic [1:0]        rresp;
  logic              rvalid;
  logic [(8*N)-1:0]  wdata;
  logic [(I-1):0]    wid;
  logic              wlast;
  logic              wready;
  logic [N-1:0]      wstrb;
  logic              wvalid;


  // --------------------------------------------------------------------
  //
  default clocking cb @(posedge aclk);
    output  arid;
    output  araddr;
    output  arburst;
    output  arcache;
    output  awid;
    output  arlen;
    output  arlock;
    output  arprot;
    output  arqos;
    input   arready;
    output  arregion;
    output  arsize;
    output  arvalid;
    output  awaddr;
    output  awburst;
    output  awcache;
    output  awlen;
    output  awlock;
    output  awprot;
    output  awqos;
    input   awready;
    output  awregion;
    output  awsize;
    output  awvalid;
    output  bready;
    input   bid;
    input   bresp;
    input   bvalid;
    input   rdata;
    input   rid;
    input   rlast;
    output  rready;
    input   rresp;
    input   rvalid;
    output  wdata;
    output  wlast;
    input   wready;
    output  wstrb;
    output  wvalid;
    input   aresetn;
    input   aclk;
  endclocking


  // --------------------------------------------------------------------
  //
  assign axi4_s.arid     = arid;
  assign axi4_s.araddr   = araddr;
  assign axi4_s.arburst  = arburst;
  assign axi4_s.arcache  = arcache;
  assign axi4_s.awid     = awid;
  assign axi4_s.arlen    = arlen;
  assign axi4_s.arlock   = arlock;
  assign axi4_s.arprot   = arprot;
  assign axi4_s.arqos    = arqos;
  assign arready         = axi4_s.arready;
  assign axi4_s.arregion = arregion;
  assign axi4_s.arsize   = arsize;
  assign axi4_s.arvalid  = arvalid;
  assign axi4_s.awaddr   = awaddr;
  assign axi4_s.awburst  = awburst;
  assign axi4_s.awcache  = awcache;
  assign axi4_s.awlen    = awlen;
  assign axi4_s.awlock   = awlock;
  assign axi4_s.awprot   = awprot;
  assign axi4_s.awqos    = awqos;
  assign awready         = axi4_s.awready;
  assign axi4_s.awregion = awregion;
  assign axi4_s.awsize   = awsize;
  assign axi4_s.awvalid  = awvalid;
  assign axi4_s.bready   = bready;
  assign bid             = axi4_s.bid;
  assign bresp           = axi4_s.bresp;
  assign bvalid          = axi4_s.bvalid;
  assign rdata           = axi4_s.rdata;
  assign rid             = axi4_s.rid;
  assign rlast           = axi4_s.rlast;
  assign axi4_s.rready   = rready;
  assign rresp           = axi4_s.rresp;
  assign rvalid          = axi4_s.rvalid;
  assign axi4_s.wdata    = wdata;
  assign axi4_s.wlast    = wlast;
  assign wready          = axi4_s.wready;
  assign axi4_s.wstrb    = wstrb;
  assign axi4_s.wvalid   = wvalid;


  // --------------------------------------------------------------------
  //
  function void
    ar_default;

    cb.araddr   <= 'bx;
    cb.arburst  <= 'bx;
    cb.arcache  <= 'bx;
    cb.arid     <= 'bx;
    cb.arlen    <= 'bx;
    cb.arlock   <= 'bx;
    cb.arprot   <= 'bx;
    cb.arqos    <= 'bx;
    cb.arregion <= 'bx;
    cb.arsize   <= 'bx;
    cb.arvalid  <= 0;

  endfunction: ar_default


  // --------------------------------------------------------------------
  //
  function void
    aw_default;

    cb.awaddr   <= 'bx;
    cb.awburst  <= 'bx;
    cb.awcache  <= 'bx;
    cb.awid     <= 'bx;
    cb.awlen    <= 'bx;
    cb.awlock   <= 'bx;
    cb.awprot   <= 'bx;
    cb.awqos    <= 'bx;
    cb.awregion <= 'bx;
    cb.awsize   <= 'bx;
    cb.awvalid  <= 0;

  endfunction: aw_default


  // --------------------------------------------------------------------
  //
  function void
    r_default;

    cb.rready <= 0;

  endfunction: r_default


  // --------------------------------------------------------------------
  //
  function void
    w_default;

    cb.wdata    <= 'bx;
    cb.wlast    <= 'bx;
    cb.wstrb    <= {N{1'b1}};
    cb.wvalid   <= 0;

  endfunction: w_default


  // --------------------------------------------------------------------
  //
  function void
    b_default;

    cb.bready   <= 0;

  endfunction: b_default


  // --------------------------------------------------------------------
  //
  function void
    init;

    ar_default();
    r_default();
    aw_default();
    w_default();
    b_default();

  endfunction: init


  // --------------------------------------------------------------------
  //
  task
    zero_cycle_delay;

    ##0;

  endtask: zero_cycle_delay


  // --------------------------------------------------------------------
  //
  import tb_bfm_pkg::*;
  import axi4_transaction_pkg::*;


  // --------------------------------------------------------------------
  //
  class ar_master_transaction_class #(A = 32, N = 8, I = 1)
    extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));

    // --------------------------------------------------------------------
    //
    task automatic
      transaction
      (
        ref T tr_h
      );

      ->this.start;

      ##(tr_h.delay_h.next());

      cb.araddr   <= tr_h.addr;
      cb.arid     <= tr_h.id;
      cb.arlen    <= tr_h.len;
      cb.arsize   <= tr_h.size;

      cb.arburst  <= tr_h.burst;
      cb.arcache  <= tr_h.cache;
      cb.arlock   <= tr_h.lock;
      cb.arprot   <= tr_h.prot;
      cb.arqos    <= tr_h.qos;
      cb.arregion <= tr_h.region;
      cb.arvalid  <= 1;

      $display("^^^ %16.t | %m | master AR transaction @ 0x%08x |", $time, tr_h.addr);

      ##1;
      wait(cb.arready);

      ##0;
      ar_default();

      ->this.done;

    endtask: transaction


  // --------------------------------------------------------------------
  //
  endclass: ar_master_transaction_class


  // --------------------------------------------------------------------
  //
  class r_master_transaction_class #(A = 32, N = 8, I = 1)
    extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));

    // --------------------------------------------------------------------
    //
    task automatic
      transaction
      (
        ref T tr_h
      );

      ->this.start;

      tr_h.data_h = new(tr_h.len);

      foreach(tr_h.payload_h.w[i])
      begin
        ##(tr_h.delay_h.next());
        cb.rready <= 1;
        ##1;

        wait(cb.rvalid);
        ##0;

        tr_h.data_h.w[i] = cb.rdata;

        $display("^^^ %16.t | %m | master R transaction | %d | 0x%016x |", $time, i, tr_h.data_h.w[i]);
        r_default();
      end

      ->this.done;

    endtask: transaction


  // --------------------------------------------------------------------
  //
  endclass: r_master_transaction_class


  // --------------------------------------------------------------------
  //
  class aw_master_transaction_class #(A = 32, N = 8, I = 1)
    extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));

    // --------------------------------------------------------------------
    //
    task automatic
      transaction
      (
        ref T tr_h
      );

      ->this.start;

      ##(tr_h.delay_h.next());

      cb.awaddr   <= tr_h.addr;
      cb.awid     <= tr_h.id;
      cb.awlen    <= tr_h.len;
      cb.awsize   <= tr_h.size;

      cb.awburst  <= tr_h.burst;
      cb.awcache  <= tr_h.cache;
      cb.awlock   <= tr_h.lock;
      cb.awprot   <= tr_h.prot;
      cb.awqos    <= tr_h.qos;
      cb.awregion <= tr_h.region;
      cb.awvalid  <= 1;

      $display("^^^ %16.t | %m | master AW transaction @ 0x%08x |", $time, tr_h.addr);

      ##1;
      wait(cb.awready);

      ##0;
      aw_default();

      ->this.done;

    endtask: transaction


  // --------------------------------------------------------------------
  //
  endclass: aw_master_transaction_class


  // --------------------------------------------------------------------
  //
  class w_master_transaction_class #(A = 32, N = 8, I = 1)
    extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));

    // --------------------------------------------------------------------
    //
    task automatic
      transaction
      (
        ref T tr_h
      );

      ->this.start;

      foreach(tr_h.payload_h.w[i])
      begin
        ##(tr_h.delay_h.next());

        cb.wdata  <= tr_h.payload_h.w[i];
        // cb.wstrb  <= tr_h.strb;    // need to fix

        if(i < tr_h.payload_h.w.size - 1)
          cb.wlast   <= 0;
        else
          cb.wlast   <= 1;

        cb.wvalid <= 1;

        ##1;
        wait(cb.wready);

        ##0;
        $display("^^^ %16.t | %m | master W transaction | %d | 0x%016x |", $time, i, tr_h.payload_h.w[i]);
        w_default();
      end

      ->this.done;

    endtask: transaction


  // --------------------------------------------------------------------
  //
  endclass: w_master_transaction_class


  // --------------------------------------------------------------------
  //
  class b_master_transaction_class #(A = 32, N = 8, I = 1)
    extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));

    // --------------------------------------------------------------------
    //
    task automatic
      transaction
      (
        ref T tr_h
      );

      ->this.start;

      ##(tr_h.delay_h.next());
      cb.bready <= 1;
      ##1;

      wait(cb.bvalid);
      ##0;

      $display("^^^ %16.t | %m | master B transaction | 0x%x |", $time, cb.bresp);
      b_default();

      ->this.done;

    endtask: transaction


  // --------------------------------------------------------------------
  //
  endclass: b_master_transaction_class


  // --------------------------------------------------------------------
  //
  ar_master_transaction_class #(.A(A), .N(N), .I(I))  ar_h;
  r_master_transaction_class  #(.A(A), .N(N), .I(I))  r_h;
  aw_master_transaction_class #(.A(A), .N(N), .I(I))  aw_h;
  w_master_transaction_class #(.A(A), .N(N), .I(I))   w_h;
  b_master_transaction_class  #(.A(A), .N(N), .I(I))  b_h;

  initial
  begin
    init();
    ar_h = new;
    ar_h.init();
    r_h = new;
    r_h.init();
    aw_h = new;
    aw_h.init();
    w_h = new;
    w_h.init();
    b_h = new;
    b_h.init();
  end


// --------------------------------------------------------------------
//

endinterface


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