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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
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//////////////////////////////////////////////////////////////////////

module
  tb_axi4_multi_port_memory
  #(
    A     = 32, // address bus width
    N     = 8,  // data bus width in bytes
    I     = 1,   // ID width
    PORTS,
    MAXWAITS = 256,
    type WORD_T = byte
  )
  (
    axi4_if     axi4_s[PORTS],

    input       aclk,
    input       aresetn
  );

  // --------------------------------------------------------------------
  //
  import axis_bfm_pkg::*;
  import axi4_memory_pkg::*;
  import axi4_arbiter_pkg::*;


  // --------------------------------------------------------------------
  //
  axi4_if #(.A(A), .N(N), .I(I)) axi4_bus(.*);


  // --------------------------------------------------------------------
  //
  axi4_arbiter_class #(A, N, I) arb_h;
  axi4_memory_class #(A, N, I, WORD_T) m_h;

  initial
  begin
    arb_h = new(axi4_s, axi4_bus);
    m_h = new(axi4_bus);
  end


  // --------------------------------------------------------------------
  //
  axi4_checker #(.A(A), .N(N), .MAXWAITS(MAXWAITS))
    axi4_bus_checker(.axi4_in(axi4_bus));


  // --------------------------------------------------------------------
  //
  generate
    begin: axi4_s_cherkers
      for(genvar j = 0; j < PORTS; j++)
        axi4_checker #(.A(A), .N(N), .MAXWAITS(MAXWAITS))
          axi4_checker_i(.axi4_in(axi4_s[j]));
    end
  endgenerate


// --------------------------------------------------------------------
//
endmodule