Subversion Repositories qaz_libs

//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////


interface
  axi4_if
  #(
    DATA_WIDTH = 64
  )
  (
    input                   aresetn,
    input                   aclk
  );

    wire                    arready;
    wire                    arregion;
    wire                    awready;
    wire                    awregion;
    wire                    bvalid;
    wire                    rlast;
    wire                    rvalid;
    wire                    wready;
    wire [1:0]              bresp;
    wire [1:0]              rresp;
    wire [5:0]              bid;
    wire [5:0]              rid;
    wire [DATA_WIDTH-1:0]   rdata;
    wire [7:0]              rcount;
    wire [7:0]              wcount;
    wire [2:0]              racount;
    wire [5:0]              wacount;
    wire                    arvalid;
    wire                    awvalid;
    wire                    bready;
    wire                    rready;
    wire                    wlast;
    wire                    wvalid;
    wire [1:0]              arburst;
    wire [1:0]              arlock;
    wire [2:0]              arsize;
    wire [1:0]              awburst;
    wire [1:0]              awlock;
    wire [2:0]              awsize;
    wire [2:0]              arprot;
    wire [2:0]              awprot;
    wire [31:0]             araddr;
    wire [31:0]             awaddr;
    wire [3:0]              arcache;
    wire [7:0]              arlen;
    wire [3:0]              arqos;
    wire [3:0]              awcache;
    wire [3:0]              awlen;
    wire [3:0]              awqos;
    wire [5:0]              arid;
    wire [5:0]              awid;
    wire [5:0]              wid;
    wire [DATA_WIDTH-1:0]   wdata;
    wire [DATA_WIDTH/8-1:0] wstrb;
  
  // --------------------------------------------------------------------
  //
  modport 
    master
    (
      output  arid,
      output  araddr,
      output  arburst,
      output  arcache,
      output  arlen,
      output  arlock,
      output  arprot,
      output  arqos,
      input   arready,
      output  arregion,
      output  arsize,
      output  arvalid,
      output  awaddr,
      output  awburst,
      output  awcache,
      output  awlen,
      output  awlock,
      output  awprot,
      output  awqos,
      input   awready,
      output  awregion,
      output  awsize,
      output  awvalid,
      output  bready,
      input   bresp,
      input   bvalid,
      input   rdata,
      input   rlast,
      output  rready,
      input   rresp,
      input   rvalid,
      output  wdata,
      output  wlast,
      input   wready,
      output  wstrb,
      output  wvalid,
      input   aresetn,
      input   aclk
    );
  
  modport 
    slave
    (
      input   arid,
      input   araddr,
      input   arburst,
      input   arcache,
      input   arlen,
      input   arlock,
      input   arprot,
      input   arqos,
      output  arready,
      input   arregion,
      input   arsize,
      input   arvalid,
      input   awaddr,
      input   awburst,
      input   awcache,
      input   awlen,
      input   awlock,
      input   awprot,
      input   awqos,
      output  awready,
      input   awregion,
      input   awsize,
      input   awvalid,
      input   bready,
      output  bresp,
      output  bvalid,
      output  rdata,
      output  rlast,
      input   rready,
      output  rresp,
      output  rvalid,
      input   wdata,
      input   wlast,
      output  wready,
      input   wstrb,
      input   wvalid,
      input   aresetn,
      input   aclk
    );
  
endinterface: axi4_if