Subversion Repositories qaz_libs

//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////


module tb_top();

  // --------------------------------------------------------------------
  // test bench clock & reset
  wire clk_100mhz;
  wire tb_clk = clk_100mhz;
  wire tb_rst;
  wire aclk = tb_clk;
  wire aresetn = ~tb_rst;

  tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);


  // --------------------------------------------------------------------
  //
  localparam A  = 32;
  localparam N  = 4;
  localparam MW = 3;  //  mux select width


  // --------------------------------------------------------------------
  //
  axi4_if #(.A(A), .N(N))
    axi4_s(.*);


  // --------------------------------------------------------------------
  //
  axi4_lite_register_if #(.N(N), .MW(MW))
    r_if(.*);

  assign r_if.register_in = r_if.register_out;


  // --------------------------------------------------------------------
  //
  axi4_lite_register_file #(.A(A), .N(N))
    dut(.*);


  // --------------------------------------------------------------------
  // sim models
  //  |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
  // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
  //  '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '

  // --------------------------------------------------------------------
  //
  // axi4_checker #(.A(A), .N(N), .PROTOCOL(2'b10))
  axi4_checker #(.A(A), .N(N))
    axi4_s_check(.axi4_in(axi4_s));


  // --------------------------------------------------------------------
  //
  import axi4_lite_agent_pkg::*;


  // --------------------------------------------------------------------
  //
  axi4_master_bfm_if #(.A(A), .N(N))
    tb_axi4_m(.axi4_s(axi4_s), .*);


  // --------------------------------------------------------------------
  //
  axi4_lite_agent_class #(.A(A), .N(N), .MW(MW)) bfm;

  initial
    bfm = new(tb_axi4_m, r_if);


  //  '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '
  // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
  //  |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
  // sim models
  // --------------------------------------------------------------------


  // --------------------------------------------------------------------
  //  debug wires


  // --------------------------------------------------------------------
  // test
  the_test test( tb_clk, tb_rst );

  initial
    begin

      test.run_the_test();

      $display("^^^---------------------------------");
      $display("^^^ %16.t | Testbench done.", $time);
      $display("^^^---------------------------------");

      $display("^^^---------------------------------");

      $stop();

    end

endmodule