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[/] [qaz_libs/] [trunk/] [axi4_stream_lib/] [src/] [axis_catenate.sv] - Rev 37

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//////////////////////////////////////////////////////////////////////
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//// Copyright (C) 2017 Authors and OPENCORES.ORG                 ////
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module
  axis_catenate
  #(
    N, // data bus width in bytes
    I = 1, // TID width
    D = 1, // TDEST width
    U = 1, // TUSER width
    U_IS_EOP = -1
  )
  (
    axis_if axis_in [1:0],
    axis_if axis_out,
    input   aclk,
    input   aresetn
  );

  // --------------------------------------------------------------------
  //
  wire select;
  wire axis_eop;

  defparam axis_eop_mux_i.U_IS_EOP = U_IS_EOP; // why are needed these for recursive modules?
  defparam axis_eop_mux_i.MA = 1;
  axis_eop_mux
  // axis_eop_mux #(.U_IS_EOP(U_IS_EOP), .MA(1))
    axis_eop_mux_i(.axis_in(axis_in), .*);


  // --------------------------------------------------------------------
  //  state machine binary definitions
  enum reg [1:0]
    {
      HEAD  = 2'b01,
      TAIL  = 2'b10
    } state, next_state;


  // --------------------------------------------------------------------
  //  state machine flop
  always_ff @(posedge aclk)
    if(~aresetn)
      state <= HEAD;
    else
      state <= next_state;


  // --------------------------------------------------------------------
  //  state machine
  always_comb
    case(state)
      HEAD:     if(axis_eop)
                  next_state <= TAIL;
                else
                  next_state <= HEAD;

      TAIL:     if(axis_eop)
                  next_state <= HEAD;
                else
                  next_state <= TAIL;

      default:  next_state <= HEAD;
    endcase


  // --------------------------------------------------------------------
  //
  axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_bus[1:0](.*);
  genvar j;

  generate
    if(U_IS_EOP > -1)
    begin: u_is_eop_gen
      for(j = 0; j < U; j++)
      begin: for_tuser_gen
        if(j == U_IS_EOP)
        begin: choped_tuser_gen
          assign axis_bus[0].tuser[j] = 0;
        end
        else
        begin: tuser_gen
          assign axis_bus[0].tuser[j] = axis_in[0].tuser[j];
        end
      end
    end
    else
    if(U_IS_EOP > -1)
    begin: tlast_gen
      assign axis_bus[0].tlast = axis_in[0].tlast;
    end
    else
    begin: choped_tlast_gen
      assign axis_bus[0].tlast = 0;
    end
  endgenerate


  // --------------------------------------------------------------------
  //
  assign axis_in[0].tready  = axis_bus[0].tready;
  assign axis_bus[0].tvalid = axis_in[0].tvalid;
  assign axis_bus[0].tdata  = axis_in[0].tdata;
  assign axis_bus[0].tstrb  = axis_in[0].tstrb;
  assign axis_bus[0].tkeep  = axis_in[0].tkeep;
  assign axis_bus[0].tid    = axis_in[0].tid;
  assign axis_bus[0].tdest  = axis_in[0].tdest;


  // --------------------------------------------------------------------
  //
  axis_alias
    axis_alias_i(axis_in[1], axis_bus[1]);


  // --------------------------------------------------------------------
  //
  defparam axis_mux_i.N = N; // why are needed these for recursive modules?
  defparam axis_mux_i.I = I;
  defparam axis_mux_i.D = D;
  defparam axis_mux_i.U = U;
  axis_mux
  // axis_mux #(.N(N), .I(I), .D(D), .U(U))
    axis_mux_i(.axis_in(axis_bus), .*);


  // --------------------------------------------------------------------
  //
  assign select = (state == HEAD) ? 0 : 1;


// --------------------------------------------------------------------
//
endmodule

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