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[/] [qaz_libs/] [trunk/] [axi4_stream_lib/] [src/] [axis_map_fifo.sv] - Rev 37

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2016 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////

module
  axis_map_fifo
  #(
    N,              // data bus width in bytes
    I = 1,          // TID width
    D = 1,          // TDEST width
    U = 1,          // TUSER width
    USE_TSTRB = 0,  //  set to 1 to enable, 0 to disable
    USE_TKEEP = 0,  //  set to 1 to enable, 0 to disable
    // USE_XID = 0,    //  set to 1 to enable, 0 to disable
    W = 0
  )
  (
    axis_if         axis_in,
    axis_if         axis_out,
    output  [W-1:0] wr_data,
    input   [W-1:0] rd_data,
    input           aclk,
    input           aresetn
  );

// --------------------------------------------------------------------
// synthesis translate_off
  initial
  begin
    // a_tid_unsuported:   assert(I == 0) else $fatal;
    // a_tdest_unsuported: assert(D == 0) else $fatal;
    // a_xid_unsuported: assert(USE_XID == 0) else $fatal;
    a_w: assert(W == (N * 8) + (N * USE_TSTRB) + (N * USE_TKEEP) + I + D + U + 1) else $fatal;
  end
// synthesis translate_on
// --------------------------------------------------------------------


  // --------------------------------------------------------------------
  //
  generate
    begin: assign_gen
      if(USE_TSTRB & USE_TKEEP)
      begin
        assign wr_data =
          {
            axis_in.tlast,
            axis_in.tuser,
            axis_in.tstrb,
            axis_in.tkeep,
            axis_in.tdata
          };
        assign
          {
            axis_out.tlast,
            axis_out.tuser,
            axis_out.tstrb,
            axis_out.tkeep,
            axis_out.tdata
          } = rd_data;
      end
      else if(USE_TSTRB)
      begin
        assign wr_data =
          {
            axis_in.tlast,
            axis_in.tuser,
            axis_in.tstrb,
            axis_in.tdata
          };
        assign
          {
            axis_out.tlast,
            axis_out.tuser,
            axis_out.tstrb,
            axis_out.tdata
          } = rd_data;
      end
      else if(USE_TKEEP)
      begin
        assign wr_data =
          {
            axis_in.tlast,
            axis_in.tuser,
            axis_in.tkeep,
            axis_in.tdata
          };
        assign
          {
            axis_out.tlast,
            axis_out.tuser,
            axis_out.tkeep,
            axis_out.tdata
          } = rd_data;
      end
      else
      begin
        assign wr_data =
          {
            axis_in.tlast,
            axis_in.tuser,
            axis_in.tdata
          };
        assign
          {
            axis_out.tlast,
            axis_out.tuser,
            axis_out.tdata
          } = rd_data;
      end
    end
  endgenerate


// --------------------------------------------------------------------
//
endmodule

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