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[/] [qaz_libs/] [trunk/] [axi4_stream_lib/] [src/] [axis_mux.sv] - Rev 31

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////

module
  axis_mux
  #(
    N,              // data bus width in bytes
    I = 0,          // TID width
    D = 0,          // TDEST width
    U = 1,          // TUSER width
    USE_TSTRB = 0,  //  set to 1 to enable, 0 to disable
    USE_TKEEP = 0   //  set to 1 to enable, 0 to disable
  )
  (
    input   mux_select,
    axis_if axis_0_in,
    axis_if axis_1_in,
    axis_if axis_out,
    input   axis_en,
    input   aclk,
    input   aresetn
  );

// --------------------------------------------------------------------
// synthesis translate_off
  initial
  begin
    a_tid_unsuported:   assert(I == 0) else $fatal;
    a_tdest_unsuported: assert(D == 0) else $fatal;
  end
// synthesis translate_on
// --------------------------------------------------------------------


  // --------------------------------------------------------------------
  //
  axis_if #(.N(N), .I(1), .D(1), .U(U))
    axis_mux_out(.*);

  assign axis_0_in.tready = mux_select ? 0                    : axis_mux_out.tready;
  assign axis_1_in.tready = mux_select ? axis_mux_out.tready  : 0;

  assign axis_mux_out.tvalid = mux_select ? axis_1_in.tvalid : axis_0_in.tvalid;
  assign axis_mux_out.tdata  = mux_select ? axis_1_in.tdata  : axis_0_in.tdata;
  assign axis_mux_out.tstrb  = mux_select ? axis_1_in.tstrb  : axis_0_in.tstrb;
  assign axis_mux_out.tkeep  = mux_select ? axis_1_in.tkeep  : axis_0_in.tkeep;
  assign axis_mux_out.tlast  = mux_select ? axis_1_in.tlast  : axis_0_in.tlast;
  assign axis_mux_out.tid    = mux_select ? axis_1_in.tid    : axis_0_in.tid;
  assign axis_mux_out.tdest  = mux_select ? axis_1_in.tdest  : axis_0_in.tdest;
  assign axis_mux_out.tuser  = mux_select ? axis_1_in.tuser  : axis_0_in.tuser;


  // --------------------------------------------------------------------
  //
  axis_register_slice
    #(
      .N(N),
      .I(I),
      .D(D),
      .U(U),
      .USE_TSTRB(USE_TSTRB),
      .USE_TKEEP(USE_TKEEP)
    )
    axis_register_slice_i
    (
      .axis_in(axis_mux_out), //  .slave
      .axis_out(axis_out),    //  .master
      .*
    );


  // --------------------------------------------------------------------
  //


endmodule


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