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[/] [qaz_libs/] [trunk/] [axi4_stream_lib/] [src/] [axis_register_slice.sv] - Rev 35

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////

module
  axis_register_slice
  #(
    N = 8,          // data bus width in bytes
    I = 0,          // TID width
    D = 0,          // TDEST width
    U = 1,          // TUSER width
    USE_TSTRB = 0,  //  set to 1 to enable, 0 to disable
    USE_TKEEP = 0   //  set to 1 to enable, 0 to disable
  )
  (
    axis_if axis_in,
    axis_if axis_out,
    input   aclk,
    input   aresetn
  );

// --------------------------------------------------------------------
// synthesis translate_off
  initial
  begin
    a_tid_unsuported:   assert(I == 0) else $fatal;
    a_tdest_unsuported: assert(D == 0) else $fatal;
  end
// synthesis translate_on
// --------------------------------------------------------------------


  // --------------------------------------------------------------------
  //
  localparam W = (N * 8) + (N * USE_TSTRB) + (N * USE_TKEEP) + I + D + U + 1;


  // --------------------------------------------------------------------
  //
  wire          wr_full;
  wire [W-1:0]  wr_data;
  wire          wr_en;

  wire          rd_empty;
  wire [W-1:0]  rd_data;
  wire          rd_en;

  tiny_sync_fifo #(.W(W))
    tiny_sync_fifo_i(.clk(aclk), .reset(~aresetn), .*);


  // --------------------------------------------------------------------
  //
  generate
    begin: assign_gen
      if(USE_TSTRB & USE_TKEEP)
      begin
        assign wr_data =
          {
            axis_in.tdata,
            axis_in.tlast,
            axis_in.tuser,
            axis_in.tstrb,
            axis_in.tkeep
          };
        assign
          {
            axis_out.tdata,
            axis_out.tlast,
            axis_out.tuser,
            axis_out.tstrb,
            axis_out.tkeep
          } = rd_data;
      end
      else if(USE_TSTRB)
      begin
        assign wr_data =
          {
            axis_in.tdata,
            axis_in.tlast,
            axis_in.tuser,
            axis_in.tstrb
          };
        assign
          {
            axis_out.tdata,
            axis_out.tlast,
            axis_out.tuser,
            axis_out.tstrb
          } = rd_data;
      end
      else if(USE_TKEEP)
      begin
        assign wr_data =
          {
            axis_in.tdata,
            axis_in.tlast,
            axis_in.tuser,
            axis_in.tkeep
          };
        assign
          {
            axis_out.tdata,
            axis_out.tlast,
            axis_out.tuser,
            axis_out.tkeep
          } = rd_data;
      end
      else
      begin
        assign wr_data =
          {
            axis_in.tdata,
            axis_in.tlast,
            axis_in.tuser
          };
        assign
          {
            axis_out.tdata,
            axis_out.tlast,
            axis_out.tuser
          } = rd_data;
      end
    end
  endgenerate


  // --------------------------------------------------------------------
  //
  assign axis_in.tready   = ~wr_full;
  assign wr_en            = axis_in.tvalid & ~wr_full;
  assign axis_out.tvalid  = ~rd_empty;
  assign rd_en            = axis_out.tready & ~rd_empty;


// --------------------------------------------------------------------
//
endmodule

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