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[/] [qaz_libs/] [trunk/] [axi4_stream_lib/] [syn/] [src/] [axis_if.sv] - Rev 31

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////


interface
  axis_if
  #(
    N = 8,  // data bus width in bytes
    I = 1,  // TID width
    D = 1,  // TDEST width
    U = 1   // TUSER width
  )
  (
    input             aclk,
    input             aresetn
  );
    wire              tvalid;
    wire              tready;
    wire  [(8*N)-1:0] tdata;
    wire  [N-1:0]     tstrb;
    wire  [N-1:0]     tkeep;
    wire              tlast;
    wire  [I-1:0]     tid;
    wire  [D-1:0]     tdest;
    wire  [U-1:0]     tuser;


// --------------------------------------------------------------------
// synthesis translate_off
    default clocking cb_m @(posedge aclk iff aresetn);
      output  tvalid;
      input   tready;
      output  tdata;
      output  tstrb;
      output  tkeep;
      output  tlast;
      output  tid;
      output  tdest;
      output  tuser;
    endclocking


    // --------------------------------------------------------------------
    //
    clocking cb_s @(posedge aclk iff aresetn);
      input   tvalid;
      output  tready;
      input   tdata;
      input   tstrb;
      input   tkeep;
      input   tlast;
      input   tid;
      input   tdest;
      input   tuser;
    endclocking


    // --------------------------------------------------------------------
    //
    modport
      master
      (
        input     aresetn,
        input     aclk,
        output    tvalid,
        input     tready,
        output    tdata,
        output    tstrb,
        output    tkeep,
        output    tlast,
        output    tid,
        output    tdest,
        output    tuser,
        clocking  cb_m
      );


    // --------------------------------------------------------------------
    //
    modport
      slave
      (
        input     aresetn,
        input     aclk,
        input     tvalid,
        output    tready,
        input     tdata,
        input     tstrb,
        input     tkeep,
        input     tlast,
        input     tid,
        input     tdest,
        input     tuser,
        clocking  cb_s
      );


// synthesis translate_on
// --------------------------------------------------------------------


endinterface: axis_if


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