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[/] [qaz_libs/] [trunk/] [basal/] [sim/] [tests/] [tb_fifo/] [fifo_driver.svh] - Rev 44

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2018 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////

class fifo_driver
  extends uvm_driver #(fifo_sequence_item);
   `uvm_component_utils(fifo_driver)

  // --------------------------------------------------------------------
  virtual fifo_if #(.W(W), .D(D)) vif;

  //--------------------------------------------------------------------
  function void set_default;
    vif.cb.wr_en <= 0;
    vif.cb.rd_en <= 0;
    vif.cb.wr_data <= 'x;
  endfunction: set_default

  //--------------------------------------------------------------------
  virtual task run_phase(uvm_phase phase);
    fifo_sequence_item item;
    super.run_phase(phase);

    set_default();

    forever
    begin
      wait(~vif.cb.reset);
      vif.zero_cycle_delay();
      seq_item_port.get_next_item(item);

      repeat(item.delay) @(vif.cb);

      if((item.command == FIFO_WR) || (item.command == FIFO_BOTH))
      begin
        if(vif.wr_full)
          `uvm_error(get_name(), "writing to full FIFO!")
        vif.cb.wr_data <= item.wr_data;
        vif.cb.wr_en <= 1;
      end

      if((item.command == FIFO_RD) || (item.command == FIFO_BOTH))
      begin
        if(vif.rd_empty)
          `uvm_error(get_name(), "reading empty FIFO!")
        item.rd_data = vif.cb.rd_data;
        vif.cb.rd_en <= 1;
      end

      @(vif.cb);
      item.wr_full = vif.wr_full;
      item.rd_empty = vif.rd_empty;
      item.count = vif.count;
      set_default();
      seq_item_port.item_done();
    end
  endtask : run_phase

  //--------------------------------------------------------------------
  function new(string name, uvm_component parent);
    super.new(name, parent);
  endfunction

// --------------------------------------------------------------------
endclass : fifo_driver

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