OpenCores
URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

[/] [qaz_libs/] [trunk/] [scripts/] [sim_procs.do] - Rev 23

Go to most recent revision | Compare with Previous | Blame | View Log

# //////////////////////////////////////////////////////////////////////
# ////                                                              ////
# //// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
# ////                                                              ////
# //// This source file may be used and distributed without         ////
# //// restriction provided that this copyright statement is not    ////
# //// removed from the file and that any derivative work contains  ////
# //// the original copyright notice and the associated disclaimer. ////
# ////                                                              ////
# //// This source file is free software; you can redistribute it   ////
# //// and/or modify it under the terms of the GNU Lesser General   ////
# //// Public License as published by the Free Software Foundation; ////
# //// either version 2.1 of the License, or (at your option) any   ////
# //// later version.                                               ////
# ////                                                              ////
# //// This source is distributed in the hope that it will be       ////
# //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
# //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
# //// PURPOSE.  See the GNU Lesser General Public License for more ////
# //// details.                                                     ////
# ////                                                              ////
# //// You should have received a copy of the GNU Lesser General    ////
# //// Public License along with this source; if not, download it   ////
# //// from http://www.opencores.org/lgpl.shtml                     ////
# ////                                                              ////
# //////////////////////////////////////////////////////////////////////


# ------------------------------------
#
proc sim_compile_all { target } {

  global env

  echo "INFO: compiling $target rtl"
  
  foreach filename [glob -nocomplain -directory ../../libs/${target}_verilog/ *.f] {
    echo "INFO: compiling $filename"
    vlog -f $filename
  }
  
  foreach filename [glob -nocomplain -directory ../../libs/${target}_VHDL/ *.f] {
    echo "INFO: compiling $filename"
    vcom -explicit -f $filename
  }
}


# ------------------------------------
#
proc sim_run_sim {  } {

  if {[file exists ./sim.do]} {
    do ./sim.do
  } elseif {[file exists ../../libs/sim.do]} {
    do ../../libs/sim.do
  } elseif {[file exists ../../libs/altera_sim.f]} {
    vsim -novopt -f ../../libs/altera_sim.f -l transcript.txt work.tb_top
  } elseif {[file exists ../../libs/xilinx_sim.f]} {
    vsim -novopt -f ../../libs/xilinx_sim.f -l transcript.txt work.tb_top work.glbl
  }
  
  if { [file exists ./wave.do] } {
    do ./wave.do
  }
}


# ------------------------------------
#
proc sim_run_test {  } {

  global env

  # unique setup
  if { [file exists ./setup_test.do] } {
    do ./setup_test.do
  }

  if { [info exists env(MAKEFILE_TEST_RUN)] } {
    vlog +define+MAKEFILE_TEST_RUN ../../src/tb_top.v
  } else {
    sim_run_sim
  }

  run -all
}


# ------------------------------------
#
proc sim_restart {  } {

  global env

  # work in progress files to compile
  if { [file exists ./wip.do] } {
    echo "INFO: found ./wip.do"
    do ./wip.do
  }
    
  if { [string equal nodesign [runStatus]] } {
    sim_run_sim
  } else {
    restart -force
  }

  run -all
}


# ------------------------------------
#
proc make_lib { lib {rebuild 0} } {

  if {[file exists $lib/_info]} {
    echo "INFO: Simulation library $lib already exists"
    
    if { $rebuild != 0 } {
      echo "INFO: Rebuilding library. Deleting ./$lib and recompiling all"
      quit -sim
      file delete -force ./$lib
      vlib $lib
      vmap $lib $lib
    }
    
  } else {
      vlib $lib
      vmap $lib $lib
  }
}

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.