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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2019 Authors and OPENCORES.ORG                 ////
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//// This source file may be used and distributed without         ////
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//// This source file is free software; you can redistribute it   ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//////////////////////////////////////////////////////////////////////

module
  avf_line_buffer_row #(N, W, AW, EOL_TO_PASS)
  (
    axis_if axis_in,
    axis_if axis_out,
    input   enable,
    output  zero_pad,
    output  initialized,
    input   aclk,
    input   aresetn
  );

  // --------------------------------------------------------------------
  wire in_eol = axis_in.tlast & axis_in.tready & axis_in.tvalid;
  wire in_eof = axis_in.tuser[2] & axis_in.tready & axis_in.tvalid;
  wire primed;

  // --------------------------------------------------------------------
  generate
  begin: counter_gen
    if(EOL_TO_PASS == 0)
    begin: first_line_gen // don't let any EOL pass through.
      // ---------------- // The trailing FIFO is primed by the first line.
      assign primed = in_eol;
    end
    else
    begin: remainder_lines_gen
      // --------------------------------------------------------------------
      reg [$clog2(EOL_TO_PASS)-1:0] eol_count;
      assign primed = (eol_count == EOL_TO_PASS) & in_eol;

      always_ff @(posedge aclk)
        if(~aresetn | primed)
          eol_count <= 0;
        else if(in_eol)
          eol_count <= eol_count + 1;
    end
  end
  endgenerate

  // --------------------------------------------------------------------
  localparam UB = $clog2(AW*2);
  localparam D = 2**UB;

  // --------------------------------------------------------------------
  wire [UB:0] count;
  wire wr_full;
  wire rd_empty;
  wire [W-1:0] wr_data = {axis_in.tlast, axis_in.tuser, axis_in.tdata};
  wire wr_en = axis_in.tready & axis_in.tvalid;
  wire rd_en = axis_out.tready & axis_out.tvalid;
  wire [W-1:0] rd_data;
  assign {axis_out.tlast, axis_out.tuser, axis_out.tdata} = rd_data;

  sync_fifo #(W, D) fifo_i(.clk(aclk), .reset(~aresetn), .*);

  // --------------------------------------------------------------------
  enum reg [3:0]
    {
      PRIME       = 4'b0001,
      INITIALIZED = 4'b0010,
      READY       = 4'b0100,
      FLUSH       = 4'b1000
    } state, next_state;

  // --------------------------------------------------------------------
  always_ff @(posedge aclk)
    if(~aresetn)
      state <= PRIME;
    else
      state <= next_state;

  // --------------------------------------------------------------------
  always_comb
    case(state)
      PRIME:        if(primed)
                      next_state = INITIALIZED;
                    else
                      next_state = PRIME;

      INITIALIZED:  if(enable)
                      next_state = READY;
                    else
                      next_state = INITIALIZED;

      READY:        if(in_eof)
                      next_state = FLUSH;
                    else
                      next_state = READY;

      FLUSH:        if(rd_empty)
                      next_state = PRIME;
                    else
                      next_state = FLUSH;

      default:      next_state = PRIME;
    endcase

  // --------------------------------------------------------------------
  generate
    if(EOL_TO_PASS == 0) // no pass through for trailing FIFO
    begin: first_line_gen
      assign axis_out.tvalid = ~rd_empty & ((state == READY) | (state == FLUSH));
    end
    else
    begin: remainder_lines_gen
      assign axis_out.tvalid = ~rd_empty & ((state == PRIME) | (state == READY) | (state == FLUSH));
    end
  endgenerate

  // --------------------------------------------------------------------
  assign axis_in.tready = ~wr_full & ((state == PRIME) | (state == READY));
  assign zero_pad = (state == PRIME) | (state == INITIALIZED);
  assign initialized = (state == INITIALIZED);

// --------------------------------------------------------------------
endmodule