################################################################ # This is a generated script based on design: zync # # Though there are limitations about the generated script, # the main purpose of this utility is to make learning # IP Integrator Tcl commands easier. ################################################################ namespace eval _tcl { proc get_script_folder {} { set script_path [file normalize [info script]] set script_folder [file dirname $script_path] return $script_folder } } variable script_folder set script_folder [_tcl::get_script_folder] ################################################################ # Check if script is running in correct Vivado version. ################################################################ set scripts_vivado_version 2016.2 set current_vivado_version [version -short] if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { puts "" catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} return 1 } ################################################################ # START ################################################################ # To test this script, run the following commands from Vivado Tcl console: # source zync_script.tcl # If there is no project opened, this script will create a # project, but make sure you do not have an existing project # <./myproj/project_1.xpr> in the current working folder. set list_projs [get_projects -quiet] if { $list_projs eq "" } { create_project project_1 myproj -part xc7z020clg484-1 set_property BOARD_PART em.avnet.com:zed:part0:1.3 [current_project] } # CHANGE DESIGN NAME HERE set design_name zync # If you do not already have an existing IP Integrator design open, # you can create a design using the following command: # create_bd_design $design_name # Creating design if needed set errMsg "" set nRet 0 set cur_design [current_bd_design -quiet] set list_cells [get_bd_cells -quiet] if { ${design_name} eq "" } { # USE CASES: # 1) Design_name not set set errMsg "Please set the variable to a non-empty value." set nRet 1 } elseif { ${cur_design} ne "" && ${list_cells} eq "" } { # USE CASES: # 2): Current design opened AND is empty AND names same. # 3): Current design opened AND is empty AND names diff; design_name NOT in project. # 4): Current design opened AND is empty AND names diff; design_name exists in project. if { $cur_design ne $design_name } { common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." set design_name [get_property NAME $cur_design] } common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { # USE CASES: # 5) Current design opened AND has components AND same names. set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." set nRet 1 } elseif { [get_files -quiet ${design_name}.bd] ne "" } { # USE CASES: # 6) Current opened design, has components, but diff names, design_name exists in project. # 7) No opened design, design_name exists in project. set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." set nRet 2 } else { # USE CASES: # 8) No opened design, design_name not in project. # 9) Current opened design, has components, but diff names, design_name not in project. common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." create_bd_design $design_name common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." current_bd_design $design_name } common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." if { $nRet != 0 } { catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} return $nRet } ################################################################## # DESIGN PROCs ################################################################## # Procedure to create entire design; Provide argument to make # procedure reusable. If parentCell is "", will use root. proc create_root_design { parentCell } { variable script_folder if { $parentCell eq "" } { set parentCell [get_bd_cells /] } # Get object for parentCell set parentObj [get_bd_cells $parentCell] if { $parentObj == "" } { catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} return } # Make sure parentObj is hier blk set parentType [get_property TYPE $parentObj] if { $parentType ne "hier" } { catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} return } # Save current instance; Restore later set oldCurInst [current_bd_instance .] # Set parent object as current current_bd_instance $parentObj # Create interface ports set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ] set M00_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M00_AXI ] set_property -dict [ list \ CONFIG.ADDR_WIDTH {32} \ CONFIG.DATA_WIDTH {32} \ CONFIG.NUM_READ_OUTSTANDING {8} \ CONFIG.NUM_WRITE_OUTSTANDING {8} \ CONFIG.PROTOCOL {AXI4LITE} \ ] $M00_AXI # Create ports set FCLK_CLK0 [ create_bd_port -dir O -type clk FCLK_CLK0 ] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {M00_AXI} \ ] $FCLK_CLK0 set peripheral_aresetn [ create_bd_port -dir O -from 0 -to 0 -type rst peripheral_aresetn ] # Create instance: axi_interconnect_0, and set properties set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] set_property -dict [ list \ CONFIG.NUM_MI {1} \ ] $axi_interconnect_0 # Create instance: proc_sys_reset_0, and set properties set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] # Create instance: processing_system7_0, and set properties set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ] set_property -dict [ list \ CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \ CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \ CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {10.000000} \ CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \ CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \ CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \ CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \ CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \ CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \ CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \ CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {50.000000} \ CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \ CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \ CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \ CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {50.000000} \ CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \ CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {666.666667} \ CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \ CONFIG.PCW_CAN0_CAN0_IO {} \ CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC {External} \ CONFIG.PCW_CAN0_PERIPHERAL_ENABLE {0} \ CONFIG.PCW_CAN1_CAN1_IO {} \ CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC {External} \ CONFIG.PCW_CAN1_PERIPHERAL_ENABLE {0} \ CONFIG.PCW_CAN_PERIPHERAL_CLKSRC {IO PLL} \ CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \ CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \ CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ {100} \ CONFIG.PCW_CLK0_FREQ {100000000} \ CONFIG.PCW_CLK1_FREQ {10000000} \ CONFIG.PCW_CLK2_FREQ {10000000} \ CONFIG.PCW_CLK3_FREQ {10000000} \ CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \ CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \ CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \ CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \ CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {33.333333} \ CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \ CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \ CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \ CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \ CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \ CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \ CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR(0)/LPR(32)} \ CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15} \ CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2} \ CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \ CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \ CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0} \ CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0} \ CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0} \ CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0} \ CONFIG.PCW_DDR_PRIORITY_READPORT_0 {} \ CONFIG.PCW_DDR_PRIORITY_READPORT_2 {} \ CONFIG.PCW_DDR_PRIORITY_WRITEPORT_0 {} \ CONFIG.PCW_DDR_PRIORITY_WRITEPORT_2 {} \ CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \ CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2} \ CONFIG.PCW_ENET0_ENET0_IO {} \ CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \ CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {1} \ CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \ CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {0} \ CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \ CONFIG.PCW_ENET0_RESET_ENABLE {0} \ CONFIG.PCW_ENET0_RESET_IO {} \ CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \ CONFIG.PCW_ENET1_GRP_MDIO_IO {} \ CONFIG.PCW_ENET_RESET_ENABLE {0} \ CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \ CONFIG.PCW_ENET_RESET_SELECT {} \ CONFIG.PCW_FTM_CTI_IN1 {} \ CONFIG.PCW_FTM_CTI_IN3 {} \ CONFIG.PCW_FTM_CTI_OUT1 {} \ CONFIG.PCW_FTM_CTI_OUT3 {} \ CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \ CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \ CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0} \ CONFIG.PCW_I2C0_GRP_INT_ENABLE {0} \ CONFIG.PCW_I2C0_GRP_INT_IO {} \ CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {0} \ CONFIG.PCW_I2C0_RESET_ENABLE {0} \ CONFIG.PCW_I2C0_RESET_IO {} \ CONFIG.PCW_I2C1_I2C1_IO {} \ CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \ CONFIG.PCW_I2C_RESET_ENABLE {1} \ CONFIG.PCW_I2C_RESET_POLARITY {Active Low} \ CONFIG.PCW_I2C_RESET_SELECT {} \ CONFIG.PCW_NAND_NAND_IO {} \ CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \ CONFIG.PCW_NOR_GRP_CS0_IO {} \ CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \ CONFIG.PCW_NOR_GRP_SRAM_CS0_IO {} \ CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \ CONFIG.PCW_NOR_GRP_SRAM_INT_IO {} \ CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \ CONFIG.PCW_NOR_SRAM_CS0_T_CEOE {1} \ CONFIG.PCW_NOR_SRAM_CS0_T_PC {1} \ CONFIG.PCW_NOR_SRAM_CS0_T_RC {2} \ CONFIG.PCW_NOR_SRAM_CS0_T_TR {1} \ CONFIG.PCW_NOR_SRAM_CS0_T_WC {2} \ CONFIG.PCW_NOR_SRAM_CS0_T_WP {1} \ CONFIG.PCW_NOR_SRAM_CS0_WE_TIME {0} \ CONFIG.PCW_NOR_SRAM_CS1_T_CEOE {1} \ CONFIG.PCW_NOR_SRAM_CS1_T_PC {1} \ CONFIG.PCW_NOR_SRAM_CS1_T_RC {2} \ CONFIG.PCW_NOR_SRAM_CS1_T_TR {1} \ CONFIG.PCW_NOR_SRAM_CS1_T_WC {2} \ CONFIG.PCW_NOR_SRAM_CS1_T_WP {1} \ CONFIG.PCW_NOR_SRAM_CS1_WE_TIME {0} \ CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.063} \ CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.062} \ CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.065} \ CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.083} \ CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {-0.007} \ CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {-0.010} \ CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.006} \ CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.048} \ CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {IO PLL} \ CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {8} \ CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ {200} \ CONFIG.PCW_PERIPHERAL_BOARD_PRESET {part0} \ CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \ CONFIG.PCW_PJTAG_PJTAG_IO {} \ CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \ CONFIG.PCW_QSPI_GRP_IO1_IO {} \ CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL} \ CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {8} \ CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \ CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200.000000} \ CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \ CONFIG.PCW_SD0_GRP_CD_ENABLE {1} \ CONFIG.PCW_SD0_GRP_CD_IO {MIO 47} \ CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \ CONFIG.PCW_SD0_GRP_POW_IO {} \ CONFIG.PCW_SD1_GRP_POW_ENABLE {0} \ CONFIG.PCW_SD1_GRP_POW_IO {} \ CONFIG.PCW_SD1_PERIPHERAL_ENABLE {0} \ CONFIG.PCW_SD1_SD1_IO {} \ CONFIG.PCW_SPI0_GRP_SS1_ENABLE {0} \ CONFIG.PCW_SPI0_GRP_SS1_IO {} \ CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {0} \ CONFIG.PCW_SPI0_SPI0_IO {} \ CONFIG.PCW_SPI1_GRP_SS1_ENABLE {0} \ CONFIG.PCW_SPI1_GRP_SS1_IO {} \ CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0} \ CONFIG.PCW_SPI1_SPI1_IO {} \ CONFIG.PCW_TRACE_GRP_2BIT_ENABLE {0} \ CONFIG.PCW_TRACE_GRP_2BIT_IO {} \ CONFIG.PCW_TRACE_GRP_4BIT_ENABLE {0} \ CONFIG.PCW_TRACE_GRP_4BIT_IO {} \ CONFIG.PCW_TRACE_INTERNAL_WIDTH {2} \ CONFIG.PCW_TRACE_PERIPHERAL_ENABLE {0} \ CONFIG.PCW_TRACE_TRACE_IO {} \ CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ {50} \ CONFIG.PCW_UART0_BAUD_RATE {115200} \ CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \ CONFIG.PCW_UART0_GRP_FULL_IO {} \ CONFIG.PCW_UART1_BAUD_RATE {115200} \ CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \ CONFIG.PCW_UART1_GRP_FULL_IO {} \ CONFIG.PCW_USB0_USB0_IO {} \ CONFIG.PCW_USB1_USB1_IO {} \ CONFIG.PCW_USE_CROSS_TRIGGER {0} \ CONFIG.PCW_WDT_PERIPHERAL_CLKSRC {CPU_1X} \ CONFIG.PCW_WDT_PERIPHERAL_DIVISOR0 {1} \ CONFIG.PCW_WDT_PERIPHERAL_ENABLE {0} \ CONFIG.PCW_WDT_PERIPHERAL_FREQMHZ {133.333333} \ CONFIG.PCW_WDT_WDT_IO {