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https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk
Subversion Repositories sdr_ctrl
[/] [sdr_ctrl/] [trunk/] [verif/] [run/] [run_modelsim] - Rev 45
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#!/bin/csh -f## test all programs with SDRAM CONTROLLER#set failedm = 0;set all_testsm = 0;set sdr_tests =(basic_test1 )#set misc_tests=( )echo " Compiling with MODELSIM in $1 $2 Mode "./compile.modelsim $1 $2 | tee ../log/$1_$2_complie.logif ($status != 0) thenecho "#### Compile : FAILED"echo ""cat ../log/complie.logexitelseecho "#### Compile : PASSED"endifecho ""echo "###########################################"echo " Runing test programs "echo "###########################################"set i = 0;echo "###########################################"foreach run_test ($sdr_tests)@ i += 1;#echo ""echo "### Running test ${i}: ${run_test}"vsim -do run.do -c tb_$1 +${run_test} | tee ../log/run.logif ($status != 0) thencat ../log/run.logexitelse if (`tail ../log/run.log | grep PASSED` == "") thenecho "### test ${i}: ${run_test} --> FAILED"@ failedm += 1;@ all_testsm += 1;elseecho "### test ${i}: ${run_test} --> PASSED"@ all_testsm += 1;endifmv ../log/run.log ../log/$1_$2_${run_test}.logendecho "###########################################"set i = 0;echo ""echo "###########################################"echo "### Test Logs "foreach run_test ($sdr_tests)@ i += 1;echo " test ${i}: ../log/$1_$2_${run_test}.log"endecho "###########################################"echo ""echo "###########################################"echo "### Test Summary "echo "### "echo "### Failed $failedm of $all_testsm $2 tests"echo "###########################################"
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