OpenCores
URL https://opencores.org/ocsvn/spacewire_light/spacewire_light/trunk

Subversion Repositories spacewire_light

[/] [spacewire_light/] [trunk/] [sim/] [ghdl/] [Makefile] - Rev 2

Go to most recent revision | Compare with Previous | Blame | View Log

#
# Makefile for building and running RTL simulation with GHDL.
#
# Simulation has been tested with GHDL 0.29.
# GHDL is available from http://ghdl.free.fr/
#

GHDL = ghdl
RTLDIR = ../../rtl/vhdl
TBDIR  = ../../bench/vhdl

.PHONY: default test_spwlink test_streamtest clean

default:
        @echo "Targets:"
        @echo "  make spwlink_tb        Build default spwlink testbench"
        @echo "  make spwlink_tb_all    Build spwlink mega testbench"
        @echo "  make test_spwlink      Run spwlink mega testbench"
        @echo "  make streamtest_tb     Build spwstream testbench"
        @echo "  make test_streamtest   Run spwstream testbench"
        @echo "  make clean             Remove build files"

SPWLINK_VHDL = $(RTLDIR)/spwpkg.vhd    \
               $(RTLDIR)/spwlink.vhd   \
               $(RTLDIR)/spwrecv.vhd   \
               $(RTLDIR)/spwxmit.vhd   \
               $(RTLDIR)/spwxmit_fast.vhd \
               $(RTLDIR)/spwrecvfront_generic.vhd \
               $(RTLDIR)/spwrecvfront_fast.vhd

SPWSTREAM_VHDL = $(SPWLINK_VHDL) \
                 $(RTLDIR)/spwstream.vhd \
                 $(RTLDIR)/spwram.vhd

spwlink_tb: $(TBDIR)/spwlink_tb.vhd $(SPWLINK_VHDL)
        $(GHDL) -c $^ -e spwlink_tb

spwlink_tb_all: $(TBDIR)/spwlink_tb_all.vhd $(TBDIR)/spwlink_tb.vhd $(SPWLINK_VHDL)
        $(GHDL) -c $^ -e spwlink_tb_all

test_spwlink: spwlink_tb_all
        $(GHDL) -r spwlink_tb_all --assert-level=error

streamtest_tb: $(TBDIR)/streamtest_tb.vhd $(RTLDIR)/streamtest.vhd $(SPWSTREAM_VHDL)
        $(GHDL) -c $^ -e streamtest_tb

test_streamtest: streamtest_tb
        $(GHDL) -r streamtest_tb --assert-level=error

clean:
        $(GHDL) --clean
        $(RM) e~spwlink_tb.o e~spwlink_tb_all.o e~streamtest_tb.o

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.