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[/] [spi_master_slave/] [trunk/] [syn/] [spi_master_atlys_top.syr] - Rev 20

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Release 13.1 - xst O.40d (nt)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.09 secs
 
--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.09 secs
 
--> Reading design: spi_master_atlys_top.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "spi_master_atlys_top.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "spi_master_atlys_top"
Output Format                      : NGC
Target Device                      : xc6slx45-2-csg324

---- Source Options
Top Module Name                    : spi_master_atlys_top
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Gray
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : No
ROM Extraction                     : No
Shift Register Extraction          : NO
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Shift Register Minimum Size        : 2
Use DSP Block                      : Auto
Automatic Register Balancing       : No

---- Target Options
LUT Combining                      : Area
Reduce Control Sets                : Auto
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Auto
Use Synchronous Set                : Auto
Use Synchronous Reset              : Auto
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 2
Power Reduction                    : NO
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
DSP48 Utilization Ratio            : 100
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_slave.vhd" into library work
Parsing entity <spi_slave>.
Parsing architecture <rtl> of entity <spi_slave>.
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 347: Case choice must be a locally static expression
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 355: Case choice must be a locally static expression
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 364: Case choice must be a locally static expression
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" into library work
Parsing entity <spi_master>.
Parsing architecture <rtl> of entity <spi_master>.
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" Line 503: Case choice must be a locally static expression
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" Line 511: Case choice must be a locally static expression
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" Line 519: Case choice must be a locally static expression
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" Line 528: Case choice must be a locally static expression
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\grp_debouncer.vhd" into library work
Parsing entity <grp_debouncer>.
Parsing architecture <rtl> of entity <grp_debouncer>.
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" into library work
Parsing entity <spi_master_atlys_top>.
Parsing architecture <behavioral> of entity <spi_master_atlys_top>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating entity <spi_master_atlys_top> (architecture <behavioral>) from library <work>.

Elaborating entity <spi_master> (architecture <rtl>) with generics from library <work>.

Elaborating entity <spi_slave> (architecture <rtl>) with generics from library <work>.

Elaborating entity <grp_debouncer> (architecture <rtl>) with generics from library <work>.

Elaborating entity <grp_debouncer> (architecture <rtl>) with generics from library <work>.
INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 456. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 517. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 567. Case statement is complete. others clause is never selected
WARNING:HDLCompiler:634 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 174: Net <dbg[3]> does not have a driver.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <spi_master_atlys_top>.
    Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd".
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port <sh_reg_dbg_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port <sck_ena_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port <sck_ena_ce_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port <do_transfer_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port <wren_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port <rx_bit_reg_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port <core_clk_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port <core_n_clk_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port <core_ce_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port <core_n_ce_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 202: Output port <sh_reg_dbg_o> of the instance <Inst_spi_slave_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 202: Output port <do_transfer_o> of the instance <Inst_spi_slave_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 202: Output port <wren_o> of the instance <Inst_spi_slave_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 202: Output port <rx_bit_next_o> of the instance <Inst_spi_slave_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 221: Output port <strb_o> of the instance <Inst_sw_debouncer> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 230: Output port <strb_o> of the instance <Inst_btn_debouncer> is unconnected or connected to loadless signal.
WARNING:Xst:2935 - Signal 'dbg<3:0>', unconnected in block 'spi_master_atlys_top', is tied to its initial value (0000).
    Found 1-bit register for signal <samp_ce_gen_proc.clk_cnt>.
    Found 1-bit register for signal <fsm_ce>.
    Found 1-bit register for signal <fsm_ce_gen_proc.clk_cnt>.
    Found 1-bit register for signal <clear>.
    Found 8-bit register for signal <led_o>.
    Found 4-bit register for signal <m_wr_st_reg>.
    Found 3-bit register for signal <s_wr_st_reg>.
    Found 3-bit register for signal <s_rd_st_reg>.
    Found 1-bit register for signal <spi_wren_reg_m>.
    Found 8-bit register for signal <spi_di_reg_m>.
    Found 1-bit register for signal <spi_rst_reg>.
    Found 1-bit register for signal <spi_ssel_reg>.
    Found 8-bit register for signal <sw_reg>.
    Found 6-bit register for signal <btn_reg>.
    Found 1-bit register for signal <spi_wren_reg_s>.
    Found 8-bit register for signal <spi_di_reg_s>.
    Found 8-bit register for signal <s_do_1_reg>.
    Found 8-bit register for signal <s_do_2_reg>.
    Found 8-bit register for signal <s_do_3_reg>.
    Found 1-bit register for signal <samp_ce>.
    Found finite state machine <FSM_2> for signal <s_rd_st_reg>.
    -----------------------------------------------------------------------
    | States             | 7                                              |
    | Transitions        | 20                                             |
    | Inputs             | 2                                              |
    | Outputs            | 3                                              |
    | Clock              | gclk_i (rising_edge)                           |
    | Reset              | spi_ssel_o (positive)                          |
    | Reset type         | synchronous                                    |
    | Reset State        | st_reset                                       |
    | Power Up State     | st_reset                                       |
    | Encoding           | Gray                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_0> for signal <m_wr_st_reg>.
    -----------------------------------------------------------------------
    | States             | 11                                             |
    | Transitions        | 36                                             |
    | Inputs             | 11                                             |
    | Outputs            | 10                                             |
    | Clock              | gclk_i (rising_edge)                           |
    | Reset              | clear (positive)                               |
    | Reset type         | synchronous                                    |
    | Reset State        | st_reset                                       |
    | Power Up State     | st_reset                                       |
    | Encoding           | Gray                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
INFO:Xst:1799 - State st_wait_spi_ack_2 is never reached in FSM <s_wr_st_reg>.
    Found finite state machine <FSM_1> for signal <s_wr_st_reg>.
    -----------------------------------------------------------------------
    | States             | 8                                              |
    | Transitions        | 20                                             |
    | Inputs             | 5                                              |
    | Outputs            | 9                                              |
    | Clock              | gclk_i (rising_edge)                           |
    | Reset              | spi_ssel_o (positive)                          |
    | Reset type         | synchronous                                    |
    | Reset State        | st_reset                                       |
    | Power Up State     | st_reset                                       |
    | Encoding           | Gray                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit adder for signal <samp_ce_gen_proc.clk_cnt[0]_PWR_4_o_add_1_OUT<0>> created at line 273.
    Found 1-bit adder for signal <fsm_ce_gen_proc.clk_cnt[0]_PWR_4_o_add_3_OUT<0>> created at line 287.
    Found 8-bit comparator equal for signal <_n0380> created at line 359
    Found 6-bit comparator equal for signal <_n0400> created at line 362
    Summary:
        inferred   2 Adder/Subtractor(s).
        inferred  71 D-type flip-flop(s).
        inferred   2 Comparator(s).
        inferred   5 Multiplexer(s).
        inferred   3 Finite State Machine(s).
Unit <spi_master_atlys_top> synthesized.

Synthesizing Unit <spi_master>.
    Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master.vhd".
        N = 8
        CPOL = '0'
        CPHA = '0'
        PREFETCH = 3
        SPI_2X_CLK_DIV = 1
    Found 1-bit register for signal <spi_2x_ce_gen_proc.clk_cnt>.
    Found 1-bit register for signal <core_clk>.
    Found 1-bit register for signal <core_n_clk>.
    Found 1-bit register for signal <core_ce>.
    Found 1-bit register for signal <core_n_ce>.
    Found 1-bit register for signal <rx_bit_reg>.
    Found 1-bit register for signal <do_valid_A>.
    Found 1-bit register for signal <do_valid_B>.
    Found 1-bit register for signal <do_valid_C>.
    Found 1-bit register for signal <do_valid_D>.
    Found 1-bit register for signal <do_valid_o_reg>.
    Found 1-bit register for signal <di_req_o_A>.
    Found 1-bit register for signal <di_req_o_B>.
    Found 1-bit register for signal <di_req_o_C>.
    Found 1-bit register for signal <di_req_o_D>.
    Found 1-bit register for signal <di_req_o_reg>.
    Found 8-bit register for signal <di_reg>.
    Found 1-bit register for signal <wren>.
    Found 4-bit register for signal <state_reg>.
    Found 8-bit register for signal <sh_reg>.
    Found 1-bit register for signal <ssel_ena_reg>.
    Found 8-bit register for signal <do_buffer_reg>.
    Found 1-bit register for signal <do_transfer_reg>.
    Found 1-bit register for signal <di_req_reg>.
    Found 1-bit register for signal <wr_ack_reg>.
    Found 1-bit register for signal <sck_ena_reg>.
    Found 1-bit register for signal <spi_clk_reg>.
    Found 1-bit register for signal <spi_2x_ce>.
    Found 1-bit adder for signal <spi_2x_ce_gen_proc.clk_cnt[0]_PWR_7_o_add_1_OUT<0>> created at line 328.
    Found 4-bit subtractor for signal <GND_7_o_GND_7_o_sub_12_OUT<3:0>> created at line 526.
    Found 4-bit comparator greater for signal <state_reg[3]_GND_7_o_LessThan_20_o> created at line 519
    Found 4-bit comparator greater for signal <GND_7_o_state_reg[3]_LessThan_21_o> created at line 519
    Found 4-bit comparator greater for signal <state_reg[3]_GND_7_o_LessThan_22_o> created at line 528
    Found 4-bit comparator greater for signal <GND_7_o_state_reg[3]_LessThan_23_o> created at line 528
    Summary:
        inferred   2 Adder/Subtractor(s).
        inferred  52 D-type flip-flop(s).
        inferred   4 Comparator(s).
        inferred  13 Multiplexer(s).
Unit <spi_master> synthesized.

Synthesizing Unit <spi_slave>.
    Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_slave.vhd".
        N = 8
        CPOL = '0'
        CPHA = '0'
        PREFETCH = 3
    Found 4-bit register for signal <state_reg>.
    Found 1-bit register for signal <do_valid_B>.
    Found 1-bit register for signal <do_valid_C>.
    Found 1-bit register for signal <do_valid_D>.
    Found 1-bit register for signal <do_valid_o_reg>.
    Found 1-bit register for signal <di_req_o_A>.
    Found 1-bit register for signal <di_req_o_B>.
    Found 1-bit register for signal <di_req_o_C>.
    Found 1-bit register for signal <di_req_o_D>.
    Found 1-bit register for signal <di_req_o_reg>.
    Found 8-bit register for signal <di_reg>.
    Found 1-bit register for signal <wren>.
    Found 8-bit register for signal <sh_reg>.
    Found 8-bit register for signal <do_buffer_reg>.
    Found 1-bit register for signal <do_transfer_reg>.
    Found 1-bit register for signal <di_req_reg>.
    Found 1-bit register for signal <wr_ack_reg>.
    Found 1-bit register for signal <tx_bit_reg>.
    Found 1-bit register for signal <do_valid_A>.
    Found 4-bit subtractor for signal <GND_8_o_GND_8_o_sub_6_OUT<3:0>> created at line 362.
    Found 4-bit comparator greater for signal <state_reg[3]_GND_8_o_LessThan_9_o> created at line 355
    Found 4-bit comparator greater for signal <GND_8_o_state_reg[3]_LessThan_10_o> created at line 355
    Found 4-bit comparator greater for signal <state_reg[3]_GND_8_o_LessThan_11_o> created at line 364
    Found 4-bit comparator greater for signal <GND_8_o_state_reg[3]_LessThan_12_o> created at line 364
    Summary:
        inferred   1 Adder/Subtractor(s).
        inferred  43 D-type flip-flop(s).
        inferred   4 Comparator(s).
        inferred  22 Multiplexer(s).
Unit <spi_slave> synthesized.

Synthesizing Unit <grp_debouncer_1>.
    Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/grp_debouncer.vhd".
        N = 8
        CNT_VAL = 200
    Found 8-bit register for signal <reg_A>.
    Found 8-bit register for signal <reg_B>.
    Found 8-bit register for signal <reg_out>.
    Found 8-bit register for signal <cnt_reg>.
    Found 9-bit adder for signal <n0024> created at line 162.
    Found 8-bit comparator not equal for signal <n0008> created at line 184
    Found 8-bit comparator not equal for signal <n0010> created at line 190
    Summary:
        inferred   1 Adder/Subtractor(s).
        inferred  32 D-type flip-flop(s).
        inferred   2 Comparator(s).
Unit <grp_debouncer_1> synthesized.

Synthesizing Unit <grp_debouncer_2>.
    Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/grp_debouncer.vhd".
        N = 6
        CNT_VAL = 200
    Found 6-bit register for signal <reg_A>.
    Found 6-bit register for signal <reg_B>.
    Found 6-bit register for signal <reg_out>.
    Found 8-bit register for signal <cnt_reg>.
    Found 9-bit adder for signal <n0024> created at line 162.
    Found 6-bit comparator not equal for signal <n0008> created at line 184
    Found 6-bit comparator not equal for signal <n0010> created at line 190
    Summary:
        inferred   1 Adder/Subtractor(s).
        inferred  26 D-type flip-flop(s).
        inferred   2 Comparator(s).
Unit <grp_debouncer_2> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 7
 1-bit adder                                           : 3
 4-bit subtractor                                      : 2
 9-bit adder                                           : 2
# Registers                                            : 72
 1-bit register                                        : 48
 4-bit register                                        : 2
 6-bit register                                        : 4
 8-bit register                                        : 18
# Comparators                                          : 14
 4-bit comparator greater                              : 8
 6-bit comparator equal                                : 1
 6-bit comparator not equal                            : 2
 8-bit comparator equal                                : 1
 8-bit comparator not equal                            : 2
# Multiplexers                                         : 40
 1-bit 2-to-1 multiplexer                              : 13
 4-bit 2-to-1 multiplexer                              : 12
 8-bit 2-to-1 multiplexer                              : 15
# FSMs                                                 : 3

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

WARNING:Xst:1710 - FF/Latch <di_reg_2> (without init value) has a constant value of 0 in block <Inst_spi_slave_port>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <di_reg_3> (without init value) has a constant value of 0 in block <Inst_spi_slave_port>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <di_reg_5> (without init value) has a constant value of 0 in block <Inst_spi_slave_port>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <spi_di_reg_s_2> has a constant value of 0 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <spi_di_reg_s_3> has a constant value of 0 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <spi_di_reg_s_5> has a constant value of 0 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process.

Synthesizing (advanced) Unit <grp_debouncer_1>.
The following registers are absorbed into counter <cnt_reg>: 1 register on signal <cnt_reg>.
Unit <grp_debouncer_1> synthesized (advanced).

Synthesizing (advanced) Unit <grp_debouncer_2>.
The following registers are absorbed into counter <cnt_reg>: 1 register on signal <cnt_reg>.
Unit <grp_debouncer_2> synthesized (advanced).

Synthesizing (advanced) Unit <spi_master>.
The following registers are absorbed into counter <spi_2x_ce_gen_proc.clk_cnt_0>: 1 register on signal <spi_2x_ce_gen_proc.clk_cnt_0>.
Unit <spi_master> synthesized (advanced).

Synthesizing (advanced) Unit <spi_master_atlys_top>.
The following registers are absorbed into counter <samp_ce_gen_proc.clk_cnt_0>: 1 register on signal <samp_ce_gen_proc.clk_cnt_0>.
The following registers are absorbed into counter <fsm_ce_gen_proc.clk_cnt_0>: 1 register on signal <fsm_ce_gen_proc.clk_cnt_0>.
Unit <spi_master_atlys_top> synthesized (advanced).

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 2
 4-bit subtractor                                      : 2
# Counters                                             : 5
 1-bit up counter                                      : 3
 8-bit up counter                                      : 2
# Registers                                            : 205
 Flip-Flops                                            : 205
# Comparators                                          : 14
 4-bit comparator greater                              : 8
 6-bit comparator equal                                : 1
 6-bit comparator not equal                            : 2
 8-bit comparator equal                                : 1
 8-bit comparator not equal                            : 2
# Multiplexers                                         : 46
 1-bit 2-to-1 multiplexer                              : 20
 4-bit 2-to-1 multiplexer                              : 12
 8-bit 2-to-1 multiplexer                              : 14
# FSMs                                                 : 3

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1293 - FF/Latch <spi_di_reg_s_2> has a constant value of 0 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <spi_di_reg_s_3> has a constant value of 0 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <spi_di_reg_s_5> has a constant value of 0 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2261 - The FF/Latch <di_reg_2> in Unit <spi_slave> is equivalent to the following 2 FFs/Latches, which will be removed : <di_reg_3> <di_reg_5> 
WARNING:Xst:1710 - FF/Latch <di_reg_2> (without init value) has a constant value of 0 in block <spi_slave>. This FF/Latch will be trimmed during the optimization process.
Optimizing FSM <FSM_2> on signal <s_rd_st_reg[1:3]> with Gray encoding.
--------------------------------------
 State                    | Encoding
--------------------------------------
 st_reset                 | 000
 st_wait_spi_do_valid_1   | 001
 st_wait_spi_n_do_valid_1 | 011
 st_wait_spi_do_valid_2   | 010
 st_wait_spi_n_do_valid_2 | 110
 st_wait_spi_do_valid_3   | 111
 st_wait_spi_n_do_valid_3 | 101
--------------------------------------
Optimizing FSM <FSM_0> on signal <m_wr_st_reg[1:4]> with Gray encoding.
----------------------------------
 State                | Encoding
----------------------------------
 st_reset             | 0000
 st_wait_spi_idle     | 0001
 st_wait_new_switch   | 0011
 st_send_spi_data_sw  | 0110
 st_wait_spi_ack_sw   | 0111
 st_send_spi_data_1   | 0010
 st_wait_spi_ack_1    | 0100
 st_wait_spi_di_req_2 | 0101
 st_wait_spi_ack_2    | 1100
 st_wait_spi_di_req_3 | 1101
 st_wait_spi_ack_3    | 1111
----------------------------------
Optimizing FSM <FSM_1> on signal <s_wr_st_reg[1:3]> with Gray encoding.
------------------------------------
 State                  | Encoding
------------------------------------
 st_reset               | 000
 st_wait_spi_start      | 001
 st_wait_spi_di_req_2   | 011
 st_wait_spi_ack_2      | unreached
 st_wait_spi_do_valid_1 | 010
 st_wait_spi_di_req_3   | 110
 st_wait_spi_ack_3      | 111
 st_wait_spi_end        | 101
------------------------------------
WARNING:Xst:1426 - The value init of the FF/Latch spi_di_reg_s_6 hinder the constant cleaning in the block spi_master_atlys_top.
   You should achieve better results by setting this init to 1.
WARNING:Xst:1426 - The value init of the FF/Latch spi_di_reg_s_4 hinder the constant cleaning in the block spi_master_atlys_top.
   You should achieve better results by setting this init to 1.
WARNING:Xst:1426 - The value init of the FF/Latch spi_di_reg_s_0 hinder the constant cleaning in the block spi_master_atlys_top.
   You should achieve better results by setting this init to 1.
WARNING:Xst:1426 - The value init of the FF/Latch spi_di_reg_s_7 hinder the constant cleaning in the block spi_master_atlys_top.
   You should achieve better results by setting this init to 1.
INFO:Xst:2261 - The FF/Latch <spi_di_reg_s_0> in Unit <spi_master_atlys_top> is equivalent to the following 3 FFs/Latches, which will be removed : <spi_di_reg_s_4> <spi_di_reg_s_6> <spi_di_reg_s_7> 

Optimizing unit <spi_master_atlys_top> ...

Optimizing unit <grp_debouncer_1> ...

Optimizing unit <grp_debouncer_2> ...

Optimizing unit <spi_master> ...

Optimizing unit <spi_slave> ...
WARNING:Xst:1293 - FF/Latch <fsm_ce> has a constant value of 1 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <samp_ce> has a constant value of 1 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <samp_ce_gen_proc.clk_cnt_0> has a constant value of 0 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <fsm_ce_gen_proc.clk_cnt_0> has a constant value of 0 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <Inst_spi_master_port/spi_2x_ce_gen_proc.clk_cnt_0> has a constant value of 0 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <Inst_spi_master_port/spi_2x_ce> has a constant value of 1 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2261 - The FF/Latch <Inst_spi_slave_port/di_reg_7> in Unit <spi_master_atlys_top> is equivalent to the following 3 FFs/Latches, which will be removed : <Inst_spi_slave_port/di_reg_6> <Inst_spi_slave_port/di_reg_4> <Inst_spi_slave_port/di_reg_0> 
INFO:Xst:2261 - The FF/Latch <Inst_spi_master_port/core_clk> in Unit <spi_master_atlys_top> is equivalent to the following FF/Latch, which will be removed : <Inst_spi_master_port/core_ce> 
INFO:Xst:3203 - The FF/Latch <Inst_spi_master_port/core_clk> in Unit <spi_master_atlys_top> is the opposite to the following 2 FFs/Latches, which will be removed : <Inst_spi_master_port/core_n_clk> <Inst_spi_master_port/core_n_ce> 

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block spi_master_atlys_top, actual ratio is 1.
FlipFlop Inst_spi_slave_port/state_reg_0 has been replicated 1 time(s)
FlipFlop Inst_spi_slave_port/state_reg_1 has been replicated 1 time(s)
FlipFlop Inst_spi_slave_port/state_reg_2 has been replicated 2 time(s)

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 217
 Flip-Flops                                            : 217

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Top Level Output File Name         : spi_master_atlys_top.ngc

Primitive and Black Box Usage:
------------------------------
# BELS                             : 205
#      GND                         : 1
#      INV                         : 4
#      LUT1                        : 14
#      LUT2                        : 4
#      LUT3                        : 28
#      LUT4                        : 17
#      LUT5                        : 55
#      LUT6                        : 47
#      MUXCY                       : 14
#      MUXF7                       : 4
#      VCC                         : 1
#      XORCY                       : 16
# FlipFlops/Latches                : 217
#      FD                          : 83
#      FD_1                        : 1
#      FDC                         : 8
#      FDE                         : 111
#      FDR                         : 10
#      FDRE                        : 4
# Clock Buffers                    : 2
#      BUFG                        : 1
#      BUFGP                       : 1
# IO Buffers                       : 62
#      IBUF                        : 14
#      OBUF                        : 48

Device utilization summary:
---------------------------

Selected Device : 6slx45csg324-2 


Slice Logic Utilization: 
 Number of Slice Registers:             217  out of  54576     0%  
 Number of Slice LUTs:                  169  out of  27288     0%  
    Number used as Logic:               169  out of  27288     0%  

Slice Logic Distribution: 
 Number of LUT Flip Flop pairs used:    274
   Number with an unused Flip Flop:      57  out of    274    20%  
   Number with an unused LUT:           105  out of    274    38%  
   Number of fully used LUT-FF pairs:   112  out of    274    40%  
   Number of unique control sets:        23

IO Utilization: 
 Number of IOs:                          63
 Number of bonded IOBs:                  63  out of    218    28%  

Specific Feature Utilization:
 Number of BUFG/BUFGCTRLs:                2  out of     16    12%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
gclk_i                             | BUFGP                  | 189   |
Inst_spi_master_port/spi_clk_reg   | BUFG                   | 28    |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -2

   Minimum period: 5.283ns (Maximum Frequency: 189.286MHz)
   Minimum input arrival time before clock: 2.083ns
   Maximum output required time after clock: 7.830ns
   Maximum combinational path delay: No path found

Timing Details:
---------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'gclk_i'
  Clock period: 5.283ns (frequency: 189.286MHz)
  Total number of paths / destination ports: 1727 / 266
-------------------------------------------------------------------------
Delay:               5.283ns (Levels of Logic = 4)
  Source:            sw_reg_5 (FF)
  Destination:       btn_reg_0 (FF)
  Source Clock:      gclk_i rising
  Destination Clock: gclk_i rising

  Data Path: sw_reg_5 to btn_reg_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              3   0.525   1.196  sw_reg_5 (sw_reg_5)
     LUT6:I1->O            2   0.254   0.834  _n038082 (_n038081)
     LUT6:I4->O            3   0.250   0.766  _n038083 (_n0380)
     LUT5:I4->O            6   0.254   0.876  _n0418_inv1_rstpot (_n0418_inv1_rstpot)
     LUT3:I2->O            1   0.254   0.000  btn_reg_0_dpot (btn_reg_0_dpot)
     FDE:D                     0.074          btn_reg_0
    ----------------------------------------
    Total                      5.283ns (1.611ns logic, 3.672ns route)
                                       (30.5% logic, 69.5% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_spi_master_port/spi_clk_reg'
  Clock period: 4.344ns (frequency: 230.203MHz)
  Total number of paths / destination ports: 214 / 36
-------------------------------------------------------------------------
Delay:               2.172ns (Levels of Logic = 2)
  Source:            Inst_spi_slave_port/state_reg_1_1 (FF)
  Destination:       Inst_spi_slave_port/tx_bit_reg (FF)
  Source Clock:      Inst_spi_master_port/spi_clk_reg rising
  Destination Clock: Inst_spi_master_port/spi_clk_reg falling

  Data Path: Inst_spi_slave_port/state_reg_1_1 to Inst_spi_slave_port/tx_bit_reg
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              2   0.525   1.156  Inst_spi_slave_port/state_reg_1_1 (Inst_spi_slave_port/state_reg_1_1)
     LUT6:I1->O            1   0.254   0.000  Inst_spi_slave_port/tx_bit_next3_F (N14)
     MUXF7:I0->O           1   0.163   0.000  Inst_spi_slave_port/tx_bit_next3 (Inst_spi_slave_port/tx_bit_next)
     FD_1:D                    0.074          Inst_spi_slave_port/tx_bit_reg
    ----------------------------------------
    Total                      2.172ns (1.016ns logic, 1.156ns route)
                                       (46.8% logic, 53.2% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'gclk_i'
  Total number of paths / destination ports: 14 / 14
-------------------------------------------------------------------------
Offset:              2.083ns (Levels of Logic = 1)
  Source:            sw_i<7> (PAD)
  Destination:       Inst_sw_debouncer/reg_A_7 (FF)
  Destination Clock: gclk_i rising

  Data Path: sw_i<7> to Inst_sw_debouncer/reg_A_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   1.328   0.681  sw_i_7_IBUF (sw_i_7_IBUF)
     FD:D                      0.074          Inst_sw_debouncer/reg_A_7
    ----------------------------------------
    Total                      2.083ns (1.402ns logic, 0.681ns route)
                                       (67.3% logic, 32.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'gclk_i'
  Total number of paths / destination ports: 41 / 31
-------------------------------------------------------------------------
Offset:              7.663ns (Levels of Logic = 4)
  Source:            Inst_spi_master_port/ssel_ena_reg (FF)
  Destination:       spi_miso_o (PAD)
  Source Clock:      gclk_i rising

  Data Path: Inst_spi_master_port/ssel_ena_reg to spi_miso_o
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              5   0.525   1.271  Inst_spi_master_port/ssel_ena_reg (Inst_spi_master_port/ssel_ena_reg)
     LUT5:I0->O            1   0.254   0.682  Inst_spi_slave_port/spi_miso_o2 (Inst_spi_slave_port/spi_miso_o1)
     LUT6:I5->O            2   0.254   0.834  Inst_spi_slave_port/spi_miso_o3 (Inst_spi_slave_port/spi_miso_o2)
     LUT3:I1->O            1   0.250   0.681  Inst_spi_slave_port/spi_miso_o4 (spi_miso_o_OBUF)
     OBUF:I->O                 2.912          spi_miso_o_OBUF (spi_miso_o)
    ----------------------------------------
    Total                      7.663ns (4.195ns logic, 3.468ns route)
                                       (54.7% logic, 45.3% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_spi_master_port/spi_clk_reg'
  Total number of paths / destination ports: 25 / 14
-------------------------------------------------------------------------
Offset:              7.830ns (Levels of Logic = 4)
  Source:            Inst_spi_slave_port/state_reg_0 (FF)
  Destination:       spi_miso_o (PAD)
  Source Clock:      Inst_spi_master_port/spi_clk_reg rising

  Data Path: Inst_spi_slave_port/state_reg_0 to spi_miso_o
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             22   0.525   1.442  Inst_spi_slave_port/state_reg_0 (Inst_spi_slave_port/state_reg_0)
     LUT5:I3->O            1   0.250   0.682  Inst_spi_slave_port/spi_miso_o2 (Inst_spi_slave_port/spi_miso_o1)
     LUT6:I5->O            2   0.254   0.834  Inst_spi_slave_port/spi_miso_o3 (Inst_spi_slave_port/spi_miso_o2)
     LUT3:I1->O            1   0.250   0.681  Inst_spi_slave_port/spi_miso_o4 (spi_miso_o_OBUF)
     OBUF:I->O                 2.912          spi_miso_o_OBUF (spi_miso_o)
    ----------------------------------------
    Total                      7.830ns (4.191ns logic, 3.639ns route)
                                       (53.5% logic, 46.5% route)

=========================================================================

Cross Clock Domains Report:
--------------------------

Clock to Setup on destination clock Inst_spi_master_port/spi_clk_reg
--------------------------------+---------+---------+---------+---------+
                                | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock                    |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
--------------------------------+---------+---------+---------+---------+
Inst_spi_master_port/spi_clk_reg|    3.706|         |    2.262|         |
gclk_i                          |    4.633|         |    2.169|         |
--------------------------------+---------+---------+---------+---------+

Clock to Setup on destination clock gclk_i
--------------------------------+---------+---------+---------+---------+
                                | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock                    |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
--------------------------------+---------+---------+---------+---------+
Inst_spi_master_port/spi_clk_reg|    4.416|    3.782|         |         |
gclk_i                          |    5.283|         |         |         |
--------------------------------+---------+---------+---------+---------+

=========================================================================


Total REAL time to Xst completion: 8.00 secs
Total CPU time to Xst completion: 7.33 secs
 
--> 

Total memory usage is 178696 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   29 (   0 filtered)
Number of infos    :   22 (   0 filtered)

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