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[/] [spi_master_slave/] [trunk/] [syn/] [spi_master_atlys_top.syr] - Rev 24
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Release 13.1 - xst O.40d (nt)Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.--> Parameter TMPDIR set to xst/projnav.tmpTotal REAL time to Xst completion: 0.00 secsTotal CPU time to Xst completion: 0.08 secs--> Parameter xsthdpdir set to xstTotal REAL time to Xst completion: 0.00 secsTotal CPU time to Xst completion: 0.08 secs--> Reading design: spi_master_atlys_top.prjTABLE OF CONTENTS1) Synthesis Options Summary2) HDL Parsing3) HDL Elaboration4) HDL Synthesis4.1) HDL Synthesis Report5) Advanced HDL Synthesis5.1) Advanced HDL Synthesis Report6) Low Level Synthesis7) Partition Report8) Design Summary8.1) Primitive and Black Box Usage8.2) Device utilization summary8.3) Partition Resource Summary8.4) Timing Report8.4.1) Clock Information8.4.2) Asynchronous Control Signals Information8.4.3) Timing Summary8.4.4) Timing Details8.4.5) Cross Clock Domains Report=========================================================================* Synthesis Options Summary *=========================================================================---- Source ParametersInput File Name : "spi_master_atlys_top.prj"Input Format : mixedIgnore Synthesis Constraint File : NO---- Target ParametersOutput File Name : "spi_master_atlys_top"Output Format : NGCTarget Device : xc6slx45-2-csg324---- Source OptionsTop Module Name : spi_master_atlys_topAutomatic FSM Extraction : YESFSM Encoding Algorithm : GraySafe Implementation : NoFSM Style : LUTRAM Extraction : NoROM Extraction : NoShift Register Extraction : NOResource Sharing : YESAsynchronous To Synchronous : NOShift Register Minimum Size : 2Use DSP Block : AutoAutomatic Register Balancing : No---- Target OptionsLUT Combining : AreaReduce Control Sets : AutoAdd IO Buffers : YESGlobal Maximum Fanout : 100000Add Generic Clock Buffer(BUFG) : 16Register Duplication : YESOptimize Instantiated Primitives : NOUse Clock Enable : AutoUse Synchronous Set : AutoUse Synchronous Reset : AutoPack IO Registers into IOBs : AutoEquivalent register Removal : YES---- General OptionsOptimization Goal : SpeedOptimization Effort : 2Power Reduction : NOKeep Hierarchy : NoNetlist Hierarchy : As_OptimizedRTL Output : YesGlobal Optimization : AllClockNetsRead Cores : YESWrite Timing Constraints : NOCross Clock Analysis : NOHierarchy Separator : /Bus Delimiter : <>Case Specifier : MaintainSlice Utilization Ratio : 100BRAM Utilization Ratio : 100DSP48 Utilization Ratio : 100Auto BRAM Packing : NOSlice Utilization Ratio Delta : 5==================================================================================================================================================* HDL Parsing *=========================================================================Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_slave.vhd" into library workParsing entity <spi_slave>.Parsing architecture <rtl> of entity <spi_slave>.WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 361: Case choice must be a locally static expressionWARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 369: Case choice must be a locally static expressionWARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 378: Case choice must be a locally static expressionParsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" into library workParsing entity <spi_master>.Parsing architecture <rtl> of entity <spi_master>.WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" Line 505: Case choice must be a locally static expressionWARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" Line 513: Case choice must be a locally static expressionWARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" Line 521: Case choice must be a locally static expressionWARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" Line 530: Case choice must be a locally static expressionParsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\grp_debouncer.vhd" into library workParsing entity <grp_debouncer>.Parsing architecture <rtl> of entity <grp_debouncer>.Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" into library workParsing entity <spi_master_atlys_top>.Parsing architecture <rtl> of entity <spi_master_atlys_top>.=========================================================================* HDL Elaboration *=========================================================================Elaborating entity <spi_master_atlys_top> (architecture <rtl>) with generics from library <work>.Elaborating entity <spi_master> (architecture <rtl>) with generics from library <work>.Elaborating entity <spi_slave> (architecture <rtl>) with generics from library <work>.Elaborating entity <grp_debouncer> (architecture <rtl>) with generics from library <work>.Elaborating entity <grp_debouncer> (architecture <rtl>) with generics from library <work>.INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 460. Case statement is complete. others clause is never selectedINFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 522. Case statement is complete. others clause is never selectedINFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 572. Case statement is complete. others clause is never selected=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <spi_master_atlys_top>.Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd".N = 8CPOL = '0'CPHA = '0'PREFETCH = 3INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port <sh_reg_dbg_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port <sck_ena_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port <sck_ena_ce_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port <do_transfer_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port <wren_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port <rx_bit_reg_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port <core_clk_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port <core_n_clk_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port <core_ce_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port <core_n_ce_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 206: Output port <sh_reg_dbg_o> of the instance <Inst_spi_slave_port> is unconnected or connected to loadless signal.INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 206: Output port <do_transfer_o> of the instance <Inst_spi_slave_port> is unconnected or connected to loadless signal.INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 206: Output port <wren_o> of the instance <Inst_spi_slave_port> is unconnected or connected to loadless signal.INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 206: Output port <rx_bit_next_o> of the instance <Inst_spi_slave_port> is unconnected or connected to loadless signal.INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 225: Output port <strb_o> of the instance <Inst_sw_debouncer> is unconnected or connected to loadless signal.INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 234: Output port <strb_o> of the instance <Inst_btn_debouncer> is unconnected or connected to loadless signal.Found 1-bit register for signal <samp_ce_gen_proc.clk_cnt>.Found 1-bit register for signal <fsm_ce>.Found 1-bit register for signal <fsm_ce_gen_proc.clk_cnt>.Found 1-bit register for signal <clear>.Found 8-bit register for signal <led_o>.Found 4-bit register for signal <m_wr_st_reg>.Found 3-bit register for signal <s_wr_st_reg>.Found 3-bit register for signal <s_rd_st_reg>.Found 1-bit register for signal <spi_wren_reg_m>.Found 8-bit register for signal <spi_di_reg_m>.Found 1-bit register for signal <spi_rst_reg>.Found 1-bit register for signal <spi_ssel_reg>.Found 8-bit register for signal <sw_reg>.Found 6-bit register for signal <btn_reg>.Found 1-bit register for signal <spi_wren_reg_s>.Found 8-bit register for signal <spi_di_reg_s>.Found 8-bit register for signal <s_do_1_reg>.Found 8-bit register for signal <s_do_2_reg>.Found 8-bit register for signal <s_do_3_reg>.Found 1-bit register for signal <samp_ce>.Found finite state machine <FSM_2> for signal <s_rd_st_reg>.-----------------------------------------------------------------------| States | 7 || Transitions | 20 || Inputs | 2 || Outputs | 3 || Clock | pclk_i (rising_edge) || Reset | spi_ssel_o (positive) || Reset type | synchronous || Reset State | st_reset || Power Up State | st_reset || Encoding | Gray || Implementation | LUT |-----------------------------------------------------------------------Found finite state machine <FSM_0> for signal <m_wr_st_reg>.-----------------------------------------------------------------------| States | 11 || Transitions | 36 || Inputs | 11 || Outputs | 10 || Clock | pclk_i (rising_edge) || Reset | clear (positive) || Reset type | synchronous || Reset State | st_reset || Power Up State | st_reset || Encoding | Gray || Implementation | LUT |-----------------------------------------------------------------------INFO:Xst:1799 - State st_wait_spi_ack_2 is never reached in FSM <s_wr_st_reg>.Found finite state machine <FSM_1> for signal <s_wr_st_reg>.-----------------------------------------------------------------------| States | 8 || Transitions | 20 || Inputs | 5 || Outputs | 9 || Clock | pclk_i (rising_edge) || Reset | spi_ssel_o (positive) || Reset type | synchronous || Reset State | st_reset || Power Up State | st_reset || Encoding | Gray || Implementation | LUT |-----------------------------------------------------------------------Found 1-bit adder for signal <samp_ce_gen_proc.clk_cnt[0]_PWR_4_o_add_1_OUT<0>> created at line 277.Found 1-bit adder for signal <fsm_ce_gen_proc.clk_cnt[0]_PWR_4_o_add_3_OUT<0>> created at line 291.Found 8-bit comparator equal for signal <_n0380> created at line 363Found 6-bit comparator equal for signal <_n0400> created at line 366Summary:inferred 2 Adder/Subtractor(s).inferred 71 D-type flip-flop(s).inferred 2 Comparator(s).inferred 5 Multiplexer(s).inferred 3 Finite State Machine(s).Unit <spi_master_atlys_top> synthesized.Synthesizing Unit <spi_master>.Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master.vhd".N = 8CPOL = '0'CPHA = '0'PREFETCH = 3SPI_2X_CLK_DIV = 1Found 1-bit register for signal <spi_2x_ce_gen_proc.clk_cnt>.Found 1-bit register for signal <core_clk>.Found 1-bit register for signal <core_n_clk>.Found 1-bit register for signal <core_ce>.Found 1-bit register for signal <core_n_ce>.Found 1-bit register for signal <rx_bit_reg>.Found 1-bit register for signal <do_valid_A>.Found 1-bit register for signal <do_valid_B>.Found 1-bit register for signal <do_valid_C>.Found 1-bit register for signal <do_valid_D>.Found 1-bit register for signal <do_valid_o_reg>.Found 1-bit register for signal <di_req_o_A>.Found 1-bit register for signal <di_req_o_B>.Found 1-bit register for signal <di_req_o_C>.Found 1-bit register for signal <di_req_o_D>.Found 1-bit register for signal <di_req_o_reg>.Found 8-bit register for signal <di_reg>.Found 1-bit register for signal <wren>.Found 4-bit register for signal <state_reg>.Found 8-bit register for signal <sh_reg>.Found 1-bit register for signal <ssel_ena_reg>.Found 8-bit register for signal <do_buffer_reg>.Found 1-bit register for signal <do_transfer_reg>.Found 1-bit register for signal <di_req_reg>.Found 1-bit register for signal <wr_ack_reg>.Found 1-bit register for signal <sck_ena_reg>.Found 1-bit register for signal <spi_clk_reg>.Found 1-bit register for signal <spi_2x_ce>.Found 1-bit adder for signal <spi_2x_ce_gen_proc.clk_cnt[0]_PWR_7_o_add_1_OUT<0>> created at line 330.Found 4-bit subtractor for signal <GND_7_o_GND_7_o_sub_12_OUT<3:0>> created at line 528.Found 4-bit comparator greater for signal <state_reg[3]_GND_7_o_LessThan_20_o> created at line 521Found 4-bit comparator greater for signal <GND_7_o_state_reg[3]_LessThan_21_o> created at line 521Found 4-bit comparator greater for signal <state_reg[3]_GND_7_o_LessThan_22_o> created at line 530Found 4-bit comparator greater for signal <GND_7_o_state_reg[3]_LessThan_23_o> created at line 530Summary:inferred 2 Adder/Subtractor(s).inferred 52 D-type flip-flop(s).inferred 4 Comparator(s).inferred 13 Multiplexer(s).Unit <spi_master> synthesized.Synthesizing Unit <spi_slave>.Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_slave.vhd".N = 8CPOL = '0'CPHA = '0'PREFETCH = 3Found 1-bit register for signal <preload_miso>.Found 4-bit register for signal <state_reg>.Found 1-bit register for signal <do_valid_B>.Found 1-bit register for signal <do_valid_C>.Found 1-bit register for signal <do_valid_D>.Found 1-bit register for signal <do_valid_o_reg>.Found 1-bit register for signal <di_req_o_A>.Found 1-bit register for signal <di_req_o_B>.Found 1-bit register for signal <di_req_o_C>.Found 1-bit register for signal <di_req_o_D>.Found 1-bit register for signal <di_req_o_reg>.Found 8-bit register for signal <di_reg>.Found 1-bit register for signal <wren>.Found 8-bit register for signal <sh_reg>.Found 8-bit register for signal <do_buffer_reg>.Found 1-bit register for signal <do_transfer_reg>.Found 1-bit register for signal <di_req_reg>.Found 1-bit register for signal <wr_ack_reg>.Found 1-bit register for signal <tx_bit_reg>.Found 1-bit register for signal <do_valid_A>.Found 4-bit subtractor for signal <GND_8_o_GND_8_o_sub_6_OUT<3:0>> created at line 376.Found 4-bit comparator greater for signal <state_reg[3]_GND_8_o_LessThan_9_o> created at line 369Found 4-bit comparator greater for signal <GND_8_o_state_reg[3]_LessThan_10_o> created at line 369Found 4-bit comparator greater for signal <state_reg[3]_GND_8_o_LessThan_11_o> created at line 378Found 4-bit comparator greater for signal <GND_8_o_state_reg[3]_LessThan_12_o> created at line 378Summary:inferred 1 Adder/Subtractor(s).inferred 44 D-type flip-flop(s).inferred 4 Comparator(s).inferred 22 Multiplexer(s).Unit <spi_slave> synthesized.Synthesizing Unit <grp_debouncer_1>.Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/grp_debouncer.vhd".N = 8CNT_VAL = 200Found 8-bit register for signal <reg_A>.Found 8-bit register for signal <reg_B>.Found 1-bit register for signal <strb_reg>.Found 8-bit register for signal <reg_out>.Found 8-bit register for signal <cnt_reg>.Found 9-bit adder for signal <n0026> created at line 167.Found 8-bit comparator not equal for signal <n0009> created at line 192Found 8-bit comparator not equal for signal <n0011> created at line 194Summary:inferred 1 Adder/Subtractor(s).inferred 33 D-type flip-flop(s).inferred 2 Comparator(s).Unit <grp_debouncer_1> synthesized.Synthesizing Unit <grp_debouncer_2>.Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/grp_debouncer.vhd".N = 6CNT_VAL = 200Found 6-bit register for signal <reg_A>.Found 6-bit register for signal <reg_B>.Found 1-bit register for signal <strb_reg>.Found 6-bit register for signal <reg_out>.Found 8-bit register for signal <cnt_reg>.Found 9-bit adder for signal <n0026> created at line 167.Found 6-bit comparator not equal for signal <n0009> created at line 192Found 6-bit comparator not equal for signal <n0011> created at line 194Summary:inferred 1 Adder/Subtractor(s).inferred 27 D-type flip-flop(s).inferred 2 Comparator(s).Unit <grp_debouncer_2> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Adders/Subtractors : 71-bit adder : 34-bit subtractor : 29-bit adder : 2# Registers : 751-bit register : 514-bit register : 26-bit register : 48-bit register : 18# Comparators : 144-bit comparator greater : 86-bit comparator equal : 16-bit comparator not equal : 28-bit comparator equal : 18-bit comparator not equal : 2# Multiplexers : 401-bit 2-to-1 multiplexer : 134-bit 2-to-1 multiplexer : 128-bit 2-to-1 multiplexer : 15# FSMs : 3==================================================================================================================================================* Advanced HDL Synthesis *=========================================================================WARNING:Xst:1710 - FF/Latch <di_reg_2> (without init value) has a constant value of 0 in block <Inst_spi_slave_port>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1710 - FF/Latch <di_reg_3> (without init value) has a constant value of 0 in block <Inst_spi_slave_port>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1710 - FF/Latch <di_reg_5> (without init value) has a constant value of 0 in block <Inst_spi_slave_port>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <spi_di_reg_s_2> has a constant value of 0 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <spi_di_reg_s_3> has a constant value of 0 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <spi_di_reg_s_5> has a constant value of 0 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process.Synthesizing (advanced) Unit <grp_debouncer_1>.The following registers are absorbed into counter <cnt_reg>: 1 register on signal <cnt_reg>.Unit <grp_debouncer_1> synthesized (advanced).Synthesizing (advanced) Unit <grp_debouncer_2>.The following registers are absorbed into counter <cnt_reg>: 1 register on signal <cnt_reg>.Unit <grp_debouncer_2> synthesized (advanced).Synthesizing (advanced) Unit <spi_master>.The following registers are absorbed into counter <spi_2x_ce_gen_proc.clk_cnt_0>: 1 register on signal <spi_2x_ce_gen_proc.clk_cnt_0>.Unit <spi_master> synthesized (advanced).Synthesizing (advanced) Unit <spi_master_atlys_top>.The following registers are absorbed into counter <samp_ce_gen_proc.clk_cnt_0>: 1 register on signal <samp_ce_gen_proc.clk_cnt_0>.The following registers are absorbed into counter <fsm_ce_gen_proc.clk_cnt_0>: 1 register on signal <fsm_ce_gen_proc.clk_cnt_0>.Unit <spi_master_atlys_top> synthesized (advanced).=========================================================================Advanced HDL Synthesis ReportMacro Statistics# Adders/Subtractors : 24-bit subtractor : 2# Counters : 51-bit up counter : 38-bit up counter : 2# Registers : 208Flip-Flops : 208# Comparators : 144-bit comparator greater : 86-bit comparator equal : 16-bit comparator not equal : 28-bit comparator equal : 18-bit comparator not equal : 2# Multiplexers : 471-bit 2-to-1 multiplexer : 214-bit 2-to-1 multiplexer : 128-bit 2-to-1 multiplexer : 14# FSMs : 3==================================================================================================================================================* Low Level Synthesis *=========================================================================WARNING:Xst:1293 - FF/Latch <spi_di_reg_s_2> has a constant value of 0 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <spi_di_reg_s_3> has a constant value of 0 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <spi_di_reg_s_5> has a constant value of 0 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process.INFO:Xst:2261 - The FF/Latch <di_reg_2> in Unit <spi_slave> is equivalent to the following 2 FFs/Latches, which will be removed : <di_reg_3> <di_reg_5>WARNING:Xst:1710 - FF/Latch <di_reg_2> (without init value) has a constant value of 0 in block <spi_slave>. This FF/Latch will be trimmed during the optimization process.Optimizing FSM <FSM_2> on signal <s_rd_st_reg[1:3]> with Gray encoding.--------------------------------------State | Encoding--------------------------------------st_reset | 000st_wait_spi_do_valid_1 | 001st_wait_spi_n_do_valid_1 | 011st_wait_spi_do_valid_2 | 010st_wait_spi_n_do_valid_2 | 110st_wait_spi_do_valid_3 | 111st_wait_spi_n_do_valid_3 | 101--------------------------------------Optimizing FSM <FSM_0> on signal <m_wr_st_reg[1:4]> with Gray encoding.----------------------------------State | Encoding----------------------------------st_reset | 0000st_wait_spi_idle | 0001st_wait_new_switch | 0011st_send_spi_data_sw | 0110st_wait_spi_ack_sw | 0111st_send_spi_data_1 | 0010st_wait_spi_ack_1 | 0100st_wait_spi_di_req_2 | 0101st_wait_spi_ack_2 | 1100st_wait_spi_di_req_3 | 1101st_wait_spi_ack_3 | 1111----------------------------------Optimizing FSM <FSM_1> on signal <s_wr_st_reg[1:3]> with Gray encoding.------------------------------------State | Encoding------------------------------------st_reset | 000st_wait_spi_start | 001st_wait_spi_di_req_2 | 011st_wait_spi_ack_2 | unreachedst_wait_spi_do_valid_1 | 010st_wait_spi_di_req_3 | 110st_wait_spi_ack_3 | 111st_wait_spi_end | 101------------------------------------WARNING:Xst:1426 - The value init of the FF/Latch spi_di_reg_s_6 hinder the constant cleaning in the block spi_master_atlys_top.You should achieve better results by setting this init to 1.WARNING:Xst:1426 - The value init of the FF/Latch spi_di_reg_s_4 hinder the constant cleaning in the block spi_master_atlys_top.You should achieve better results by setting this init to 1.WARNING:Xst:1426 - The value init of the FF/Latch spi_di_reg_s_0 hinder the constant cleaning in the block spi_master_atlys_top.You should achieve better results by setting this init to 1.INFO:Xst:2261 - The FF/Latch <spi_di_reg_s_0> in Unit <spi_master_atlys_top> is equivalent to the following 2 FFs/Latches, which will be removed : <spi_di_reg_s_4> <spi_di_reg_s_6>INFO:Xst:2261 - The FF/Latch <spi_di_reg_s_1> in Unit <spi_master_atlys_top> is equivalent to the following FF/Latch, which will be removed : <spi_di_reg_s_7>Optimizing unit <spi_master_atlys_top> ...Optimizing unit <grp_debouncer_1> ...Optimizing unit <grp_debouncer_2> ...Optimizing unit <spi_master> ...Optimizing unit <spi_slave> ...WARNING:Xst:2677 - Node <Inst_sw_debouncer/strb_reg> of sequential type is unconnected in block <spi_master_atlys_top>.WARNING:Xst:2677 - Node <Inst_btn_debouncer/strb_reg> of sequential type is unconnected in block <spi_master_atlys_top>.WARNING:Xst:1293 - FF/Latch <fsm_ce> has a constant value of 1 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <samp_ce> has a constant value of 1 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <samp_ce_gen_proc.clk_cnt_0> has a constant value of 0 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <fsm_ce_gen_proc.clk_cnt_0> has a constant value of 0 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <Inst_spi_master_port/spi_2x_ce_gen_proc.clk_cnt_0> has a constant value of 0 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <Inst_spi_master_port/spi_2x_ce> has a constant value of 1 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process.INFO:Xst:2261 - The FF/Latch <Inst_spi_slave_port/di_reg_6> in Unit <spi_master_atlys_top> is equivalent to the following 2 FFs/Latches, which will be removed : <Inst_spi_slave_port/di_reg_4> <Inst_spi_slave_port/di_reg_0>INFO:Xst:2261 - The FF/Latch <Inst_spi_slave_port/di_reg_7> in Unit <spi_master_atlys_top> is equivalent to the following FF/Latch, which will be removed : <Inst_spi_slave_port/di_reg_1>INFO:Xst:2261 - The FF/Latch <Inst_spi_master_port/core_clk> in Unit <spi_master_atlys_top> is equivalent to the following FF/Latch, which will be removed : <Inst_spi_master_port/core_ce>INFO:Xst:3203 - The FF/Latch <Inst_spi_master_port/core_clk> in Unit <spi_master_atlys_top> is the opposite to the following 2 FFs/Latches, which will be removed : <Inst_spi_master_port/core_n_clk> <Inst_spi_master_port/core_n_ce>Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block spi_master_atlys_top, actual ratio is 1.FlipFlop Inst_spi_slave_port/state_reg_0 has been replicated 1 time(s)FlipFlop Inst_spi_slave_port/state_reg_1 has been replicated 1 time(s)FlipFlop Inst_spi_slave_port/state_reg_2 has been replicated 2 time(s)Final Macro Processing ...=========================================================================Final Register ReportMacro Statistics# Registers : 218Flip-Flops : 218==================================================================================================================================================* Partition Report *=========================================================================Partition Implementation Status-------------------------------No Partitions were found in this design.-------------------------------=========================================================================* Design Summary *=========================================================================Top Level Output File Name : spi_master_atlys_top.ngcPrimitive and Black Box Usage:------------------------------# BELS : 202# GND : 1# INV : 4# LUT1 : 14# LUT2 : 4# LUT3 : 28# LUT4 : 17# LUT5 : 54# LUT6 : 45# MUXCY : 14# MUXF7 : 4# VCC : 1# XORCY : 16# FlipFlops/Latches : 218# FD : 84# FD_1 : 1# FDC : 8# FDE : 110# FDP_1 : 1# FDR : 10# FDRE : 4# Clock Buffers : 3# BUFG : 1# BUFGP : 2# IO Buffers : 62# IBUF : 14# OBUF : 48Device utilization summary:---------------------------Selected Device : 6slx45csg324-2Slice Logic Utilization:Number of Slice Registers: 218 out of 54576 0%Number of Slice LUTs: 166 out of 27288 0%Number used as Logic: 166 out of 27288 0%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 272Number with an unused Flip Flop: 54 out of 272 19%Number with an unused LUT: 106 out of 272 38%Number of fully used LUT-FF pairs: 112 out of 272 41%Number of unique control sets: 24IO Utilization:Number of IOs: 64Number of bonded IOBs: 64 out of 218 29%Specific Feature Utilization:Number of BUFG/BUFGCTRLs: 3 out of 16 18%---------------------------Partition Resource Summary:---------------------------No Partitions were found in this design.---------------------------=========================================================================Timing ReportNOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORTGENERATED AFTER PLACE-and-ROUTE.Clock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+pclk_i | BUFGP | 161 |sclk_i | BUFGP | 28 |Inst_spi_master_port/spi_clk_reg | BUFG | 29 |-----------------------------------+------------------------+-------+Asynchronous Control Signals Information:----------------------------------------No asynchronous control signals found in this designTiming Summary:---------------Speed Grade: -2Minimum period: 5.283ns (Maximum Frequency: 189.286MHz)Minimum input arrival time before clock: 2.083nsMaximum output required time after clock: 7.216nsMaximum combinational path delay: No path foundTiming Details:---------------All values displayed in nanoseconds (ns)=========================================================================Timing constraint: Default period analysis for Clock 'pclk_i'Clock period: 5.283ns (frequency: 189.286MHz)Total number of paths / destination ports: 1509 / 201-------------------------------------------------------------------------Delay: 5.283ns (Levels of Logic = 4)Source: sw_reg_5 (FF)Destination: btn_reg_0 (FF)Source Clock: pclk_i risingDestination Clock: pclk_i risingData Path: sw_reg_5 to btn_reg_0Gate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------FDE:C->Q 3 0.525 1.196 sw_reg_5 (sw_reg_5)LUT6:I1->O 2 0.254 0.834 _n038082 (_n038081)LUT6:I4->O 3 0.250 0.766 _n038083 (_n0380)LUT5:I4->O 6 0.254 0.876 _n0418_inv1_rstpot (_n0418_inv1_rstpot)LUT3:I2->O 1 0.254 0.000 btn_reg_0_dpot (btn_reg_0_dpot)FDE:D 0.074 btn_reg_0----------------------------------------Total 5.283ns (1.611ns logic, 3.672ns route)(30.5% logic, 69.5% route)=========================================================================Timing constraint: Default period analysis for Clock 'sclk_i'Clock period: 3.764ns (frequency: 265.675MHz)Total number of paths / destination ports: 173 / 52-------------------------------------------------------------------------Delay: 3.764ns (Levels of Logic = 1)Source: Inst_spi_master_port/state_reg_3 (FF)Destination: Inst_spi_master_port/sh_reg_7 (FF)Source Clock: sclk_i risingDestination Clock: sclk_i risingData Path: Inst_spi_master_port/state_reg_3 to Inst_spi_master_port/sh_reg_7Gate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------FDRE:C->Q 21 0.525 1.740 Inst_spi_master_port/state_reg_3 (Inst_spi_master_port/state_reg_3)LUT6:I1->O 8 0.254 0.943 Inst_spi_master_port/_n0278_inv1 (Inst_spi_master_port/_n0278_inv)FDE:CE 0.302 Inst_spi_master_port/sh_reg_0----------------------------------------Total 3.764ns (1.081ns logic, 2.683ns route)(28.7% logic, 71.3% route)=========================================================================Timing constraint: Default period analysis for Clock 'Inst_spi_master_port/spi_clk_reg'Clock period: 4.344ns (frequency: 230.203MHz)Total number of paths / destination ports: 214 / 36-------------------------------------------------------------------------Delay: 2.172ns (Levels of Logic = 2)Source: Inst_spi_slave_port/state_reg_1_1 (FF)Destination: Inst_spi_slave_port/tx_bit_reg (FF)Source Clock: Inst_spi_master_port/spi_clk_reg risingDestination Clock: Inst_spi_master_port/spi_clk_reg fallingData Path: Inst_spi_slave_port/state_reg_1_1 to Inst_spi_slave_port/tx_bit_regGate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------FDC:C->Q 2 0.525 1.156 Inst_spi_slave_port/state_reg_1_1 (Inst_spi_slave_port/state_reg_1_1)LUT6:I1->O 1 0.254 0.000 Inst_spi_slave_port/tx_bit_next3_F (N14)MUXF7:I0->O 1 0.163 0.000 Inst_spi_slave_port/tx_bit_next3 (Inst_spi_slave_port/tx_bit_next)FD_1:D 0.074 Inst_spi_slave_port/tx_bit_reg----------------------------------------Total 2.172ns (1.016ns logic, 1.156ns route)(46.8% logic, 53.2% route)=========================================================================Timing constraint: Default OFFSET IN BEFORE for Clock 'pclk_i'Total number of paths / destination ports: 14 / 14-------------------------------------------------------------------------Offset: 2.083ns (Levels of Logic = 1)Source: sw_i<7> (PAD)Destination: Inst_sw_debouncer/reg_A_7 (FF)Destination Clock: pclk_i risingData Path: sw_i<7> to Inst_sw_debouncer/reg_A_7Gate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------IBUF:I->O 1 1.328 0.681 sw_i_7_IBUF (sw_i_7_IBUF)FD:D 0.074 Inst_sw_debouncer/reg_A_7----------------------------------------Total 2.083ns (1.402ns logic, 0.681ns route)(67.3% logic, 32.7% route)=========================================================================Timing constraint: Default OFFSET OUT AFTER for Clock 'pclk_i'Total number of paths / destination ports: 17 / 16-------------------------------------------------------------------------Offset: 5.464ns (Levels of Logic = 2)Source: Inst_spi_master_port/wren (FF)Destination: spi_mosi_o (PAD)Source Clock: pclk_i risingData Path: Inst_spi_master_port/wren to spi_mosi_oGate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------FD:C->Q 8 0.525 1.052 Inst_spi_master_port/wren (Inst_spi_master_port/wren)LUT6:I4->O 2 0.250 0.725 Inst_spi_master_port/spi_mosi_o (spi_mosi_o_OBUF)OBUF:I->O 2.912 spi_mosi_o_OBUF (spi_mosi_o)----------------------------------------Total 5.464ns (3.687ns logic, 1.777ns route)(67.5% logic, 32.5% route)=========================================================================Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_spi_master_port/spi_clk_reg'Total number of paths / destination ports: 19 / 18-------------------------------------------------------------------------Offset: 5.307ns (Levels of Logic = 2)Source: Inst_spi_slave_port/preload_miso (FF)Destination: spi_miso_o (PAD)Source Clock: Inst_spi_master_port/spi_clk_reg fallingData Path: Inst_spi_slave_port/preload_miso to spi_miso_oGate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------FDP_1:C->Q 2 0.525 0.954 Inst_spi_slave_port/preload_miso (Inst_spi_slave_port/preload_miso)LUT3:I0->O 1 0.235 0.681 Inst_spi_slave_port/Mmux_spi_miso_o11 (spi_miso_o_OBUF)OBUF:I->O 2.912 spi_miso_o_OBUF (spi_miso_o)----------------------------------------Total 5.307ns (3.672ns logic, 1.635ns route)(69.2% logic, 30.8% route)=========================================================================Timing constraint: Default OFFSET OUT AFTER for Clock 'sclk_i'Total number of paths / destination ports: 20 / 16-------------------------------------------------------------------------Offset: 7.216ns (Levels of Logic = 3)Source: Inst_spi_master_port/state_reg_2 (FF)Destination: spi_mosi_o (PAD)Source Clock: sclk_i risingData Path: Inst_spi_master_port/state_reg_2 to spi_mosi_oGate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------FDRE:C->Q 20 0.525 1.394 Inst_spi_master_port/state_reg_2 (Inst_spi_master_port/state_reg_2)LUT2:I0->O 2 0.250 1.156 Inst_spi_master_port/spi_mosi_o_SW0 (N4)LUT6:I1->O 2 0.254 0.725 Inst_spi_master_port/spi_mosi_o (spi_mosi_o_OBUF)OBUF:I->O 2.912 spi_mosi_o_OBUF (spi_mosi_o)----------------------------------------Total 7.216ns (3.941ns logic, 3.275ns route)(54.6% logic, 45.4% route)=========================================================================Cross Clock Domains Report:--------------------------Clock to Setup on destination clock Inst_spi_master_port/spi_clk_reg--------------------------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|--------------------------------+---------+---------+---------+---------+Inst_spi_master_port/spi_clk_reg| 3.682| | 2.224| |pclk_i | 3.012| | 2.135| |sclk_i | 4.633| | 3.198| |--------------------------------+---------+---------+---------+---------+Clock to Setup on destination clock pclk_i--------------------------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|--------------------------------+---------+---------+---------+---------+Inst_spi_master_port/spi_clk_reg| 2.078| | | |pclk_i | 5.283| | | |sclk_i | 3.198| | | |--------------------------------+---------+---------+---------+---------+Clock to Setup on destination clock sclk_i--------------------------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|--------------------------------+---------+---------+---------+---------+Inst_spi_master_port/spi_clk_reg| | 1.855| | |pclk_i | 3.244| | | |sclk_i | 3.764| | | |--------------------------------+---------+---------+---------+---------+=========================================================================Total REAL time to Xst completion: 6.00 secsTotal CPU time to Xst completion: 6.39 secs-->Total memory usage is 179340 kilobytesNumber of errors : 0 ( 0 filtered)Number of warnings : 28 ( 0 filtered)Number of infos : 24 ( 0 filtered)