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[/] [spi_master_slave/] [trunk/] [syn/] [spi_master_atlys_top.twr] - Rev 22

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--------------------------------------------------------------------------------
Release 13.1 Trace  (nt)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

C:\Xilinx\13.1\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 2 -n
3 -fastpaths -xml spi_master_atlys_top.twx spi_master_atlys_top.ncd -o
spi_master_atlys_top.twr spi_master_atlys_top.pcf -ucf spi_master_atlys.ucf

Design file:              spi_master_atlys_top.ncd
Physical constraint file: spi_master_atlys_top.pcf
Device,package,speed:     xc6slx45,csg324,C,-2 (PRODUCTION 1.18 2011-04-07)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.



Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock gclk_i
------------+------------+------------+------------+------------+------------------+--------+
            |Max Setup to|  Process   |Max Hold to |  Process   |                  | Clock  |
Source      | clk (edge) |   Corner   | clk (edge) |   Corner   |Internal Clock(s) | Phase  |
------------+------------+------------+------------+------------+------------------+--------+
btn_i<0>    |    3.220(R)|      SLOW  |   -1.908(R)|      FAST  |gclk_i_BUFGP      |   0.000|
btn_i<1>    |    2.732(R)|      SLOW  |   -1.473(R)|      FAST  |gclk_i_BUFGP      |   0.000|
btn_i<2>    |    2.624(R)|      SLOW  |   -1.423(R)|      FAST  |gclk_i_BUFGP      |   0.000|
btn_i<3>    |    2.466(R)|      SLOW  |   -1.367(R)|      SLOW  |gclk_i_BUFGP      |   0.000|
btn_i<4>    |    2.808(R)|      SLOW  |   -1.482(R)|      FAST  |gclk_i_BUFGP      |   0.000|
btn_i<5>    |    2.631(R)|      SLOW  |   -1.435(R)|      FAST  |gclk_i_BUFGP      |   0.000|
sw_i<0>     |    4.138(R)|      SLOW  |   -2.205(R)|      FAST  |gclk_i_BUFGP      |   0.000|
sw_i<1>     |    5.757(R)|      SLOW  |   -3.265(R)|      FAST  |gclk_i_BUFGP      |   0.000|
sw_i<2>     |    5.825(R)|      SLOW  |   -3.246(R)|      FAST  |gclk_i_BUFGP      |   0.000|
sw_i<3>     |    4.946(R)|      SLOW  |   -2.785(R)|      FAST  |gclk_i_BUFGP      |   0.000|
sw_i<4>     |    3.431(R)|      SLOW  |   -1.904(R)|      FAST  |gclk_i_BUFGP      |   0.000|
sw_i<5>     |    3.569(R)|      SLOW  |   -2.000(R)|      FAST  |gclk_i_BUFGP      |   0.000|
sw_i<6>     |    3.411(R)|      SLOW  |   -1.943(R)|      FAST  |gclk_i_BUFGP      |   0.000|
sw_i<7>     |    5.265(R)|      SLOW  |   -2.971(R)|      FAST  |gclk_i_BUFGP      |   0.000|
------------+------------+------------+------------+------------+------------------+--------+

Clock gclk_i to Pad
------------+-----------------+------------+-----------------+------------+------------------+--------+
            |Max (slowest) clk|  Process   |Min (fastest) clk|  Process   |                  | Clock  |
Destination |  (edge) to PAD  |   Corner   |  (edge) to PAD  |   Corner   |Internal Clock(s) | Phase  |
------------+-----------------+------------+-----------------+------------+------------------+--------+
dbg_o<4>    |         9.886(R)|      SLOW  |         4.102(R)|      FAST  |gclk_i_BUFGP      |   0.000|
dbg_o<5>    |         9.856(R)|      SLOW  |         4.079(R)|      FAST  |gclk_i_BUFGP      |   0.000|
dbg_o<7>    |        10.279(R)|      SLOW  |         4.343(R)|      FAST  |gclk_i_BUFGP      |   0.000|
dbg_o<8>    |        10.485(R)|      SLOW  |         4.438(R)|      FAST  |gclk_i_BUFGP      |   0.000|
dbg_o<9>    |        10.661(R)|      SLOW  |         4.583(R)|      FAST  |gclk_i_BUFGP      |   0.000|
dbg_o<10>   |        10.595(R)|      SLOW  |         4.516(R)|      FAST  |gclk_i_BUFGP      |   0.000|
dbg_o<11>   |        10.797(R)|      SLOW  |         4.632(R)|      FAST  |gclk_i_BUFGP      |   0.000|
led_o<0>    |        10.127(R)|      SLOW  |         4.227(R)|      FAST  |gclk_i_BUFGP      |   0.000|
led_o<1>    |         9.955(R)|      SLOW  |         4.135(R)|      FAST  |gclk_i_BUFGP      |   0.000|
led_o<2>    |        10.096(R)|      SLOW  |         4.211(R)|      FAST  |gclk_i_BUFGP      |   0.000|
led_o<3>    |         9.531(R)|      SLOW  |         3.887(R)|      FAST  |gclk_i_BUFGP      |   0.000|
led_o<4>    |        10.129(R)|      SLOW  |         4.244(R)|      FAST  |gclk_i_BUFGP      |   0.000|
led_o<5>    |        16.930(R)|      SLOW  |         8.194(R)|      FAST  |gclk_i_BUFGP      |   0.000|
led_o<6>    |        12.027(R)|      SLOW  |         5.407(R)|      FAST  |gclk_i_BUFGP      |   0.000|
led_o<7>    |        11.196(R)|      SLOW  |         4.818(R)|      FAST  |gclk_i_BUFGP      |   0.000|
m_do_o<0>   |         9.636(R)|      SLOW  |         3.930(R)|      FAST  |gclk_i_BUFGP      |   0.000|
m_do_o<1>   |         9.683(R)|      SLOW  |         3.987(R)|      FAST  |gclk_i_BUFGP      |   0.000|
m_do_o<2>   |         9.651(R)|      SLOW  |         3.945(R)|      FAST  |gclk_i_BUFGP      |   0.000|
m_do_o<3>   |         9.718(R)|      SLOW  |         4.091(R)|      FAST  |gclk_i_BUFGP      |   0.000|
m_do_o<4>   |         9.623(R)|      SLOW  |         4.055(R)|      FAST  |gclk_i_BUFGP      |   0.000|
m_do_o<5>   |         9.875(R)|      SLOW  |         4.135(R)|      FAST  |gclk_i_BUFGP      |   0.000|
m_do_o<6>   |         9.742(R)|      SLOW  |         4.088(R)|      FAST  |gclk_i_BUFGP      |   0.000|
m_do_o<7>   |         9.568(R)|      SLOW  |         4.000(R)|      FAST  |gclk_i_BUFGP      |   0.000|
m_state_o<0>|        11.544(R)|      SLOW  |         5.167(R)|      FAST  |gclk_i_BUFGP      |   0.000|
m_state_o<1>|        11.702(R)|      SLOW  |         5.283(R)|      FAST  |gclk_i_BUFGP      |   0.000|
m_state_o<2>|        11.667(R)|      SLOW  |         5.272(R)|      FAST  |gclk_i_BUFGP      |   0.000|
m_state_o<3>|        11.707(R)|      SLOW  |         5.314(R)|      FAST  |gclk_i_BUFGP      |   0.000|
spi_miso_o  |        11.814(R)|      SLOW  |         5.115(R)|      FAST  |gclk_i_BUFGP      |   0.000|
spi_mosi_o  |        13.768(R)|      SLOW  |         5.317(R)|      FAST  |gclk_i_BUFGP      |   0.000|
spi_sck_o   |        11.645(R)|      SLOW  |         5.148(R)|      FAST  |gclk_i_BUFGP      |   0.000|
spi_ssel_o  |        12.580(R)|      SLOW  |         5.649(R)|      FAST  |gclk_i_BUFGP      |   0.000|
------------+-----------------+------------+-----------------+------------+------------------+--------+

Clock to Setup on destination clock gclk_i
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
gclk_i         |    4.888|         |         |         |
---------------+---------+---------+---------+---------+


Analysis completed Mon Aug 29 00:08:54 2011 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 177 MB



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