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[/] [spi_master_slave/] [trunk/] [syn/] [spi_master_atlys_top_map.map] - Rev 22

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Release 13.1 Map O.40d (nt)
Xilinx Map Application Log File for Design 'spi_master_atlys_top'

Design Information
------------------
Command Line   : map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol
high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area
-equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power
off -o spi_master_atlys_top_map.ncd spi_master_atlys_top.ngd
spi_master_atlys_top.pcf 
Target Device  : xc6slx45
Target Package : csg324
Target Speed   : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date    : Mon Aug 29 00:08:18 2011

Running global optimization...
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
   (.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 9 secs 
Total CPU  time at the beginning of Placer: 9 secs 

Phase 1.1  Initial Placement Analysis
Phase 1.1  Initial Placement Analysis (Checksum:7388cd6e) REAL time: 10 secs 

Phase 2.7  Design Feasibility Check
INFO:Place:834 - Only a subset of IOs are locked. Out of 63 IOs, 47 are locked
   and 16 are not locked. If you would like to print the names of these IOs,
   please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1. 
Phase 2.7  Design Feasibility Check (Checksum:7388cd6e) REAL time: 10 secs 

Phase 3.31  Local Placement Optimization
Phase 3.31  Local Placement Optimization (Checksum:7388cd6e) REAL time: 10 secs 

Phase 4.2  Initial Placement for Architecture Specific Features
...
Phase 4.2  Initial Placement for Architecture Specific Features
(Checksum:e9015cfe) REAL time: 14 secs 

Phase 5.36  Local Placement Optimization
Phase 5.36  Local Placement Optimization (Checksum:e9015cfe) REAL time: 14 secs 

Phase 6.30  Global Clock Region Assignment
Phase 6.30  Global Clock Region Assignment (Checksum:e9015cfe) REAL time: 14 secs 

Phase 7.3  Local Placement Optimization
...
Phase 7.3  Local Placement Optimization (Checksum:fcc976fb) REAL time: 15 secs 

Phase 8.5  Local Placement Optimization
Phase 8.5  Local Placement Optimization (Checksum:fcc976fb) REAL time: 15 secs 

Phase 9.8  Global Placement
..
..
Phase 9.8  Global Placement (Checksum:4a08930d) REAL time: 15 secs 

Phase 10.5  Local Placement Optimization
Phase 10.5  Local Placement Optimization (Checksum:4a08930d) REAL time: 15 secs 

Phase 11.18  Placement Optimization
Phase 11.18  Placement Optimization (Checksum:1a1797e0) REAL time: 16 secs 

Phase 12.5  Local Placement Optimization
Phase 12.5  Local Placement Optimization (Checksum:1a1797e0) REAL time: 16 secs 

Phase 13.34  Placement Validation
Phase 13.34  Placement Validation (Checksum:bc560c6c) REAL time: 16 secs 

Total REAL time to Placer completion: 16 secs 
Total CPU  time to Placer completion: 16 secs 
Running post-placement packing...
Writing output files...

Design Summary
--------------

Design Summary:
Number of errors:      0
Number of warnings:    0
Slice Logic Utilization:
  Number of Slice Registers:                   224 out of  54,576    1%
    Number used as Flip Flops:                 224
    Number used as Latches:                      0
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                0
  Number of Slice LUTs:                        177 out of  27,288    1%
    Number used as logic:                      167 out of  27,288    1%
      Number using O6 output only:             112
      Number using O5 output only:              28
      Number using O5 and O6:                   27
      Number used as ROM:                        0
    Number used as Memory:                       4 out of   6,408    1%
      Number used as Dual Port RAM:              0
      Number used as Single Port RAM:            0
      Number used as Shift Register:             4
        Number using O6 output only:             4
        Number using O5 output only:             0
        Number using O5 and O6:                  0
    Number used exclusively as route-thrus:      6
      Number with same-slice register load:      4
      Number with same-slice carry load:         2
      Number with other load:                    0

Slice Logic Distribution:
  Number of occupied Slices:                   102 out of   6,822    1%
  Number of LUT Flip Flop pairs used:          272
    Number with an unused Flip Flop:            64 out of     272   23%
    Number with an unused LUT:                  95 out of     272   34%
    Number of fully used LUT-FF pairs:         113 out of     272   41%
    Number of unique control sets:              26
    Number of slice register sites lost
      to control set restrictions:              68 out of  54,576    1%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                        63 out of     218   28%
    Number of LOCed IOBs:                       47 out of      63   74%

Specific Feature Utilization:
  Number of RAMB16BWERs:                         0 out of     116    0%
  Number of RAMB8BWERs:                          0 out of     232    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 0 out of      32    0%
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
  Number of BUFG/BUFGMUXs:                       2 out of      16   12%
    Number used as BUFGs:                        2
    Number used as BUFGMUX:                      0
  Number of DCM/DCM_CLKGENs:                     0 out of       8    0%
  Number of ILOGIC2/ISERDES2s:                   0 out of     376    0%
  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     376    0%
  Number of OLOGIC2/OSERDES2s:                   0 out of     376    0%
  Number of BSCANs:                              0 out of       4    0%
  Number of BUFHs:                               0 out of     256    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFPLL_MCBs:                         0 out of       4    0%
  Number of DSP48A1s:                            0 out of      58    0%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                0 out of       2    0%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            0 out of       4    0%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%

Average Fanout of Non-Clock Nets:                3.18

Peak Memory Usage:  298 MB
Total REAL time to MAP completion:  17 secs 
Total CPU time to MAP completion (all processors):   17 secs 

Mapping completed.
See MAP report file "spi_master_atlys_top_map.mrp" for details.

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