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[/] [spi_master_slave/] [trunk/] [syn/] [spi_master_atlys_top_map.mrp] - Rev 20

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Release 13.1 Map O.40d (nt)
Xilinx Mapping Report File for Design 'spi_master_atlys_top'

Design Information
------------------
Command Line   : map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol
high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area
-equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power
off -o spi_master_atlys_top_map.ncd spi_master_atlys_top.ngd
spi_master_atlys_top.pcf 
Target Device  : xc6slx45
Target Package : csg324
Target Speed   : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date    : Wed Aug 10 22:56:29 2011

Design Summary
--------------
Number of errors:      0
Number of warnings:    0
Slice Logic Utilization:
  Number of Slice Registers:                   209 out of  54,576    1%
    Number used as Flip Flops:                 209
    Number used as Latches:                      0
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                0
  Number of Slice LUTs:                        145 out of  27,288    1%
    Number used as logic:                      127 out of  27,288    1%
      Number using O6 output only:              75
      Number using O5 output only:              13
      Number using O5 and O6:                   39
      Number used as ROM:                        0
    Number used as Memory:                       4 out of   6,408    1%
      Number used as Dual Port RAM:              0
      Number used as Single Port RAM:            0
      Number used as Shift Register:             4
        Number using O6 output only:             4
        Number using O5 output only:             0
        Number using O5 and O6:                  0
    Number used exclusively as route-thrus:     14
      Number with same-slice register load:     12
      Number with same-slice carry load:         2
      Number with other load:                    0

Slice Logic Distribution:
  Number of occupied Slices:                    91 out of   6,822    1%
  Number of LUT Flip Flop pairs used:          225
    Number with an unused Flip Flop:            49 out of     225   21%
    Number with an unused LUT:                  80 out of     225   35%
    Number of fully used LUT-FF pairs:          96 out of     225   42%
    Number of unique control sets:              25
    Number of slice register sites lost
      to control set restrictions:              59 out of  54,576    1%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                        63 out of     218   28%
    Number of LOCed IOBs:                       43 out of      63   68%

Specific Feature Utilization:
  Number of RAMB16BWERs:                         0 out of     116    0%
  Number of RAMB8BWERs:                          0 out of     232    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 0 out of      32    0%
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
  Number of BUFG/BUFGMUXs:                       2 out of      16   12%
    Number used as BUFGs:                        2
    Number used as BUFGMUX:                      0
  Number of DCM/DCM_CLKGENs:                     0 out of       8    0%
  Number of ILOGIC2/ISERDES2s:                   0 out of     376    0%
  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     376    0%
  Number of OLOGIC2/OSERDES2s:                   0 out of     376    0%
  Number of BSCANs:                              0 out of       4    0%
  Number of BUFHs:                               0 out of     256    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFPLL_MCBs:                         0 out of       4    0%
  Number of DSP48A1s:                            0 out of      58    0%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                0 out of       2    0%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            0 out of       4    0%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%

Average Fanout of Non-Clock Nets:                2.81

Peak Memory Usage:  303 MB
Total REAL time to MAP completion:  19 secs 
Total CPU time to MAP completion (all processors):   17 secs 

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Timing Report
Section 11 - Configuration String Information
Section 12 - Control Set Information
Section 13 - Utilization by Hierarchy

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------

Section 3 - Informational
-------------------------
INFO:Map:284 - Map is running with the multi-threading option on. Map currently
   supports the use of up to 2 processors. Based on the the user options and
   machine load, Map will use 2 processors during this run.
INFO:Xst:2261 - The FF/Latch <Inst_spi_slave_port/state_reg_0> in Unit
   <spi_master_atlys_top> is equivalent to the following FF/Latch, which will be
   removed : <Inst_spi_slave_port/state_reg_0_1> 
INFO:Xst:2261 - The FF/Latch <Inst_spi_slave_port/state_reg_1> in Unit
   <spi_master_atlys_top> is equivalent to the following FF/Latch, which will be
   removed : <Inst_spi_slave_port/state_reg_1_1> 
INFO:Xst:2261 - The FF/Latch <Inst_spi_slave_port/state_reg_2> in Unit
   <spi_master_atlys_top> is equivalent to the following 2 FFs/Latches, which
   will be removed : <Inst_spi_slave_port/state_reg_2_1>
   <Inst_spi_slave_port/state_reg_2_2> 
INFO:LIT:243 - Logical network gclk_i_BUFGP/N2 has no load.
INFO:LIT:243 - Logical network gclk_i_BUFGP/N3 has no load.
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs.
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
   0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
   1.260 Volts)
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
   (.mrp).
INFO:Place:834 - Only a subset of IOs are locked. Out of 63 IOs, 43 are locked
   and 20 are not locked. If you would like to print the names of these IOs,
   please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1. 
INFO:Pack:1650 - Map created a placed design.

Section 4 - Removed Logic Summary
---------------------------------
   2 block(s) removed
   2 block(s) optimized away
   2 signal(s) removed
  55 Block(s) redundant

Section 5 - Removed Logic
-------------------------

The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections.  If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented.  This
indentation will be repeated as a chain of related logic is removed.

To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).

The signal "gclk_i_BUFGP/N2" is sourceless and has been removed.
The signal "gclk_i_BUFGP/N3" is sourceless and has been removed.
Unused block "gclk_i_BUFGP/XST_GND" (ZERO) removed.
Unused block "gclk_i_BUFGP/XST_VCC" (ONE) removed.

Optimized Block(s):
TYPE            BLOCK
GND             XST_GND
VCC             XST_VCC

Redundant Block(s):
TYPE            BLOCK
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<6>_rt
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<5>_rt
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<4>_rt
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<3>_rt
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<2>_rt
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<1>_rt
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<6>_rt
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<5>_rt
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<4>_rt
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<3>_rt
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<2>_rt
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<1>_rt
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_xor<7>_rt
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_xor<7>_rt
INV             ][1034_3_INV_0
INV             ][269_110_INV_0
INV             ][369_165_INV_0
INV             ][373_170_INV_0
INV             ][389_183_INV_0
INV             ][397_190_INV_0
INV             ][401_194_INV_0
INV             ][402_198_INV_0
INV             ][405_200_INV_0
INV             ][409_205_INV_0
INV             ][413_210_INV_0
INV             ][417_215_INV_0
INV             ][421_220_INV_0
INV             ][425_225_INV_0
INV             ][429_230_INV_0
INV             ][441_243_INV_0
INV             ][453_254_INV_0
INV             ][461_261_INV_0
INV             ][465_265_INV_0
INV             ][469_269_INV_0
INV             ][645_378_INV_0
INV             ][649_383_INV_0
INV             ][653_387_INV_0
INV             ][657_391_INV_0
INV             ][661_395_INV_0
INV             ][665_399_INV_0
INV             ][669_403_INV_0
INV             ][673_407_INV_0
INV             ][694_422_INV_0
INV             ][729_448_INV_0
INV             ][783_487_INV_0
INV             ][791_494_INV_0
INV             ][795_498_INV_0
INV             ][799_503_INV_0
INV             ][807_509_INV_0
INV             ][840_536_INV_0
INV             ][845_539_INV_0
INV             ][882_563_INV_0
INV             ][888_569_INV_0
INV             ][923_599_INV_0
INV             ][926_603_INV_0

Section 6 - IOB Properties
--------------------------

+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type             | Direction | IO Standard          | Diff  | Drive    | Slew | Reg (s)      | Resistor | IOB      |
|                                    |                  |           |                      | Term  | Strength | Rate |              |          | Delay    |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| btn_i<0>                           | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| btn_i<1>                           | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| btn_i<2>                           | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| btn_i<3>                           | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| btn_i<4>                           | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| btn_i<5>                           | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| dbg_o<0>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| dbg_o<1>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| dbg_o<2>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| dbg_o<3>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| dbg_o<4>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| dbg_o<5>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| dbg_o<6>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| dbg_o<7>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| dbg_o<8>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| dbg_o<9>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| dbg_o<10>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| dbg_o<11>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| gclk_i                             | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| led_o<0>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| led_o<1>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| led_o<2>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| led_o<3>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| led_o<4>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| led_o<5>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| led_o<6>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| led_o<7>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| m_do_o<0>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| m_do_o<1>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| m_do_o<2>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| m_do_o<3>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| m_do_o<4>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| m_do_o<5>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| m_do_o<6>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| m_do_o<7>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| m_state_o<0>                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| m_state_o<1>                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| m_state_o<2>                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| m_state_o<3>                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| s_do_o<0>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| s_do_o<1>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| s_do_o<2>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| s_do_o<3>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| s_do_o<4>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| s_do_o<5>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| s_do_o<6>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| s_do_o<7>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| s_state_o<0>                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| s_state_o<1>                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| s_state_o<2>                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| s_state_o<3>                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| spi_miso_o                         | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| spi_mosi_o                         | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| spi_sck_o                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| spi_ssel_o                         | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
| sw_i<0>                            | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| sw_i<1>                            | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| sw_i<2>                            | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| sw_i<3>                            | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| sw_i<4>                            | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| sw_i<5>                            | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| sw_i<6>                            | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
| sw_i<7>                            | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+

Section 7 - RPMs
----------------

Section 8 - Guide Report
------------------------
Guide not run on this design.

Section 9 - Area Group and Partition Summary
--------------------------------------------

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Area Group Information
----------------------

  No area groups were found in this design.

----------------------

Section 10 - Timing Report
--------------------------
A logic-level (pre-route) timing report can be generated by using Xilinx static
timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
mapped NCD and PCF files. Please note that this timing report will be generated
using estimated delay information. For accurate numbers, please generate a
timing report with the post Place and Route NCD file.

For more information about the Timing Analyzer, consult the Xilinx Timing
Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
Command Line Tools User Guide "TRACE" chapter.

Section 11 - Configuration String Details
-----------------------------------------

Section 12 - Control Set Information
------------------------------------
+-----------------------------------------------------------------------------------------------------------------------------------+
| Clock Signal                           | Reset Signal           | Set Signal | Enable Signal  | Slice Load Count | Bel Load Count |
+-----------------------------------------------------------------------------------------------------------------------------------+
| Inst_spi_master_port/spi_clk_reg_BUFG  |                        |            |                | 6                | 11             |
| Inst_spi_master_port/spi_clk_reg_BUFG  |                        |            | lut1153_485    | 3                | 8              |
| Inst_spi_master_port/spi_clk_reg_BUFG  | ][1032_0               |            |                | 2                | 3              |
| Inst_spi_master_port/spi_clk_reg_BUFG  | ][IN_virtPIBox_530_660 |            |                | 1                | 1              |
+-----------------------------------------------------------------------------------------------------------------------------------+
| gclk_i_BUFGP                           |                        |            |                | 31               | 71             |
| gclk_i_BUFGP                           |                        |            | GLOBAL_LOGIC1  | 1                | 4              |
| gclk_i_BUFGP                           |                        |            | ][210_37       | 1                | 8              |
| gclk_i_BUFGP                           |                        |            | ][242_80       | 2                | 6              |
| gclk_i_BUFGP                           |                        |            | ][402_198      | 2                | 8              |
| gclk_i_BUFGP                           |                        |            | ][691_420      | 2                | 4              |
| gclk_i_BUFGP                           |                        |            | lut403_108     | 1                | 2              |
| gclk_i_BUFGP                           |                        |            | lut415_115     | 2                | 8              |
| gclk_i_BUFGP                           |                        |            | lut456_132     | 2                | 8              |
| gclk_i_BUFGP                           |                        |            | lut497_149     | 2                | 8              |
| gclk_i_BUFGP                           |                        |            | lut539_168     | 2                | 8              |
| gclk_i_BUFGP                           |                        |            | lut703_275     | 1                | 8              |
| gclk_i_BUFGP                           |                        |            | lut825_325     | 2                | 6              |
| gclk_i_BUFGP                           |                        |            | lut916_362     | 2                | 8              |
| gclk_i_BUFGP                           |                        |            | lut958_381     | 2                | 8              |
| gclk_i_BUFGP                           |                        |            | spi_wren_reg_m | 1                | 8              |
| gclk_i_BUFGP                           |                        |            | spi_wren_reg_s | 1                | 2              |
| gclk_i_BUFGP                           | ][1032_0               |            |                | 4                | 6              |
| gclk_i_BUFGP                           | clear                  |            |                | 2                | 4              |
| gclk_i_BUFGP                           | spi_rst_reg            |            | ][691_420      | 1                | 4              |
+-----------------------------------------------------------------------------------------------------------------------------------+
| ~Inst_spi_master_port/spi_clk_reg_BUFG |                        |            |                | 1                | 1              |
+-----------------------------------------------------------------------------------------------------------------------------------+

Section 13 - Utilization by Hierarchy
-------------------------------------
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Module                | Partition | Slices*       | Slice Reg     | LUTs          | LUTRAM        | BRAM/FIFO | DSP48A1 | BUFG  | BUFIO | BUFR  | DCM   | PLL_ADV   | Full Hierarchical Name                     |
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| spi_master_atlys_top/ |           | 64/121        | 71/209        | 109/119       | 0/4           | 0/0       | 0/0     | 1/2   | 0/0   | 0/0   | 0/0   | 0/0       | spi_master_atlys_top                       |
| +Inst_btn_debouncer   |           | 10/10         | 26/26         | 1/1           | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | 0/0       | spi_master_atlys_top/Inst_btn_debouncer    |
| +Inst_spi_master_port |           | 18/18         | 45/45         | 2/2           | 2/2           | 0/0       | 0/0     | 1/1   | 0/0   | 0/0   | 0/0   | 0/0       | spi_master_atlys_top/Inst_spi_master_port  |
| +Inst_spi_slave_port  |           | 21/21         | 35/35         | 6/6           | 2/2           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | 0/0       | spi_master_atlys_top/Inst_spi_slave_port   |
| +Inst_sw_debouncer    |           | 8/8           | 32/32         | 1/1           | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | 0/0       | spi_master_atlys_top/Inst_sw_debouncer     |
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

* Slices can be packed with basic elements from multiple hierarchies.
  Therefore, a slice will be counted in every hierarchical module
  that each of its packed basic elements belong to.
** For each column, there are two numbers reported <A>/<B>.
   <A> is the number of elements that belong to that specific hierarchical module.
   <B> is the total number of elements from that hierarchical module and any lower level
   hierarchical modules below.
*** The LUTRAM column counts all LUTs used as memory including RAM, ROM, and shift registers.

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