OpenCores
URL https://opencores.org/ocsvn/spi_master_slave/spi_master_slave/trunk

Subversion Repositories spi_master_slave

[/] [spi_master_slave/] [trunk/] [syn/] [spi_ms_atlys.gise] - Rev 20

Go to most recent revision | Compare with Previous | Blame | View Log

<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">

  <!--                                                          -->

  <!--             For tool use only. Do not edit.              -->

  <!--                                                          -->

  <!-- ProjectNavigator created generated project file.         -->

  <!-- For use in tracking generated file and other information -->

  <!-- allowing preservation of process status.                 -->

  <!--                                                          -->

  <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->

  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>

  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="spi_ms_atlys.xise"/>

  <files xmlns="http://www.xilinx.com/XMLSchema">
    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="spi_master_atlys_top.bgn" xil_pn:subbranch="FPGAConfiguration"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="spi_master_atlys_top.bit" xil_pn:subbranch="FPGAConfiguration"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="spi_master_atlys_top.bld"/>
    <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="spi_master_atlys_top.cmd_log"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="spi_master_atlys_top.drc" xil_pn:subbranch="FPGAConfiguration"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="spi_master_atlys_top.lso"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="spi_master_atlys_top.ncd" xil_pn:subbranch="Par"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="spi_master_atlys_top.ngc"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="spi_master_atlys_top.ngd"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="spi_master_atlys_top.ngr"/>
    <file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="spi_master_atlys_top.pad"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="spi_master_atlys_top.par" xil_pn:subbranch="Par"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="spi_master_atlys_top.pcf" xil_pn:subbranch="Map"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="spi_master_atlys_top.prj"/>
    <file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="spi_master_atlys_top.ptwx"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="spi_master_atlys_top.stx"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="spi_master_atlys_top.syr"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="spi_master_atlys_top.twr" xil_pn:subbranch="Par"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="spi_master_atlys_top.twx" xil_pn:subbranch="Par"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="spi_master_atlys_top.unroutes" xil_pn:subbranch="Par"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="spi_master_atlys_top.ut" xil_pn:subbranch="FPGAConfiguration"/>
    <file xil_pn:fileType="FILE_XPI" xil_pn:name="spi_master_atlys_top.xpi"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="spi_master_atlys_top.xst"/>
    <file xil_pn:fileType="FILE_NCD" xil_pn:name="spi_master_atlys_top_guide.ncd" xil_pn:origination="imported"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="spi_master_atlys_top_map.map" xil_pn:subbranch="Map"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="spi_master_atlys_top_map.mrp" xil_pn:subbranch="Map"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="spi_master_atlys_top_map.ncd" xil_pn:subbranch="Map"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="spi_master_atlys_top_map.ngm" xil_pn:subbranch="Map"/>
    <file xil_pn:fileType="FILE_PSR" xil_pn:name="spi_master_atlys_top_map.psr"/>
    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="spi_master_atlys_top_map.xrpt"/>
    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="spi_master_atlys_top_ngdbuild.xrpt"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="spi_master_atlys_top_pad.csv" xil_pn:subbranch="Par"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="spi_master_atlys_top_pad.txt" xil_pn:subbranch="Par"/>
    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="spi_master_atlys_top_par.xrpt"/>
    <file xil_pn:fileType="FILE_HTML" xil_pn:name="spi_master_atlys_top_summary.html"/>
    <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="spi_master_atlys_top_summary.xml"/>
    <file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="spi_master_atlys_top_usage.xml"/>
    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="spi_master_atlys_top_xst.xrpt"/>
    <file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
    <file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
    <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
  </files>

  <transforms xmlns="http://www.xilinx.com/XMLSchema">
    <transform xil_pn:end_ts="1313027771" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1313027771">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1313027771" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3566399560241464054" xil_pn:start_ts="1313027771">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1313027771" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2102355656976309210" xil_pn:start_ts="1313027771">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1313027771" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1313027771">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1313027771" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-1280022453574249608" xil_pn:start_ts="1313027771">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1313027771" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8977612015756273942" xil_pn:start_ts="1313027771">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1313027771" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-8317595265581962832" xil_pn:start_ts="1313027771">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1313027782" xil_pn:in_ck="-8247761554522826671" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-8195216592062898977" xil_pn:start_ts="1313027771">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="WarningsGenerated"/>
      <status xil_pn:value="ReadyToRun"/>
      <status xil_pn:value="OutOfDateForOutputs"/>
      <status xil_pn:value="OutputChanged"/>
      <outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
      <outfile xil_pn:name="spi_master_atlys_top.lso"/>
      <outfile xil_pn:name="spi_master_atlys_top.ngc"/>
      <outfile xil_pn:name="spi_master_atlys_top.ngr"/>
      <outfile xil_pn:name="spi_master_atlys_top.prj"/>
      <outfile xil_pn:name="spi_master_atlys_top.stx"/>
      <outfile xil_pn:name="spi_master_atlys_top.syr"/>
      <outfile xil_pn:name="spi_master_atlys_top.xst"/>
      <outfile xil_pn:name="spi_master_atlys_top_xst.xrpt"/>
      <outfile xil_pn:name="webtalk_pn.xml"/>
      <outfile xil_pn:name="xst"/>
    </transform>
    <transform xil_pn:end_ts="1313027782" xil_pn:in_ck="-6344801126424831697" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-4068456177828066131" xil_pn:start_ts="1313027782">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1313027787" xil_pn:in_ck="-2449764723691034422" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-177710677611610831" xil_pn:start_ts="1313027782">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="_ngo"/>
      <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
      <outfile xil_pn:name="spi_master_atlys_top.bld"/>
      <outfile xil_pn:name="spi_master_atlys_top.ngd"/>
      <outfile xil_pn:name="spi_master_atlys_top_ngdbuild.xrpt"/>
    </transform>
    <transform xil_pn:end_ts="1313027810" xil_pn:in_ck="-2449764723691034421" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-1658770934691434356" xil_pn:start_ts="1313027787">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <status xil_pn:value="OutOfDateForOutputs"/>
      <status xil_pn:value="OutputChanged"/>
      <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
      <outfile xil_pn:name="spi_master_atlys_top.pcf"/>
      <outfile xil_pn:name="spi_master_atlys_top_map.map"/>
      <outfile xil_pn:name="spi_master_atlys_top_map.mrp"/>
      <outfile xil_pn:name="spi_master_atlys_top_map.ncd"/>
      <outfile xil_pn:name="spi_master_atlys_top_map.ngm"/>
      <outfile xil_pn:name="spi_master_atlys_top_map.psr"/>
      <outfile xil_pn:name="spi_master_atlys_top_map.xrpt"/>
      <outfile xil_pn:name="spi_master_atlys_top_summary.xml"/>
      <outfile xil_pn:name="spi_master_atlys_top_usage.xml"/>
    </transform>
    <transform xil_pn:end_ts="1313027829" xil_pn:in_ck="5633518429974504804" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="7846039340612803429" xil_pn:start_ts="1313027810">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="WarningsGenerated"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
      <outfile xil_pn:name="spi_master_atlys_top.ncd"/>
      <outfile xil_pn:name="spi_master_atlys_top.pad"/>
      <outfile xil_pn:name="spi_master_atlys_top.par"/>
      <outfile xil_pn:name="spi_master_atlys_top.ptwx"/>
      <outfile xil_pn:name="spi_master_atlys_top.unroutes"/>
      <outfile xil_pn:name="spi_master_atlys_top.xpi"/>
      <outfile xil_pn:name="spi_master_atlys_top_pad.csv"/>
      <outfile xil_pn:name="spi_master_atlys_top_pad.txt"/>
      <outfile xil_pn:name="spi_master_atlys_top_par.xrpt"/>
    </transform>
    <transform xil_pn:end_ts="1313027964" xil_pn:in_ck="-5988982649231273448" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="7135157351517842893" xil_pn:start_ts="1313027946">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
      <outfile xil_pn:name="spi_master_atlys_top.bgn"/>
      <outfile xil_pn:name="spi_master_atlys_top.bit"/>
      <outfile xil_pn:name="spi_master_atlys_top.drc"/>
      <outfile xil_pn:name="spi_master_atlys_top.ut"/>
      <outfile xil_pn:name="usage_statistics_webtalk.html"/>
      <outfile xil_pn:name="webtalk.log"/>
      <outfile xil_pn:name="webtalk_pn.xml"/>
    </transform>
    <transform xil_pn:end_ts="1313027829" xil_pn:in_ck="-2449764723691034553" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1313027823">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
      <outfile xil_pn:name="spi_master_atlys_top.twr"/>
      <outfile xil_pn:name="spi_master_atlys_top.twx"/>
    </transform>
  </transforms>

</generated_project>

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.