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Subversion Repositories spi_master_slave

[/] [spi_master_slave/] [trunk/] [syn/] [spi_test_ct.wcfg] - Rev 20

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<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
   <wave_state>
   </wave_state>
   <db_ref_list>
      <db_ref path="D:/Dropbox/VHDL_training/ISE_projects/spi_ms_atlys_ct/testbench_isim_translate.wdb" id="1" type="auto">
         <top_modules>
            <top_module name="numeric_std" />
            <top_module name="std_logic_1164" />
            <top_module name="testbench" />
            <top_module name="textio" />
            <top_module name="vcomponents" />
            <top_module name="vital_primitives" />
            <top_module name="vital_timing" />
            <top_module name="vpackage" />
         </top_modules>
      </db_ref>
   </db_ref_list>
   <WVObjectSize size="21" />
   <wvobject fp_name="/testbench/dbg" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">dbg[11:0]</obj_property>
      <obj_property name="ObjectShortName">dbg[11:0]</obj_property>
      <obj_property name="Radix">HEXRADIX</obj_property>
   </wvobject>
   <wvobject fp_name="/testbench/sysclk" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">sysclk</obj_property>
      <obj_property name="ObjectShortName">sysclk</obj_property>
   </wvobject>
   <wvobject fp_name="/testbench/sw_data" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">sw_data[7:0]</obj_property>
      <obj_property name="ObjectShortName">sw_data[7:0]</obj_property>
      <obj_property name="Radix">HEXRADIX</obj_property>
   </wvobject>
   <wvobject fp_name="/testbench/btn_data" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">btn_data[5:0]</obj_property>
      <obj_property name="ObjectShortName">btn_data[5:0]</obj_property>
      <obj_property name="Radix">HEXRADIX</obj_property>
   </wvobject>
   <wvobject fp_name="/testbench/spi_ssel" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">spi_ssel</obj_property>
      <obj_property name="ObjectShortName">spi_ssel</obj_property>
   </wvobject>
   <wvobject fp_name="/testbench/spi_sck" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">spi_sck</obj_property>
      <obj_property name="ObjectShortName">spi_sck</obj_property>
   </wvobject>
   <wvobject fp_name="/testbench/spi_mosi" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">spi_mosi</obj_property>
      <obj_property name="ObjectShortName">spi_mosi</obj_property>
   </wvobject>
   <wvobject fp_name="/testbench/spi_miso" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">spi_miso</obj_property>
      <obj_property name="ObjectShortName">spi_miso</obj_property>
   </wvobject>
   <wvobject fp_name="/testbench/wren_m" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">wren_m</obj_property>
      <obj_property name="ObjectShortName">wren_m</obj_property>
   </wvobject>
   <wvobject fp_name="/testbench/wr_ack_m" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">wr_ack_m</obj_property>
      <obj_property name="ObjectShortName">wr_ack_m</obj_property>
   </wvobject>
   <wvobject fp_name="/testbench/di_req_m" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">di_req_m</obj_property>
      <obj_property name="ObjectShortName">di_req_m</obj_property>
   </wvobject>
   <wvobject fp_name="/testbench/do_valid_m" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">do_valid_m</obj_property>
      <obj_property name="ObjectShortName">do_valid_m</obj_property>
   </wvobject>
   <wvobject fp_name="/testbench/m_do_reg" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">m_do_reg[7:0]</obj_property>
      <obj_property name="ObjectShortName">m_do_reg[7:0]</obj_property>
      <obj_property name="Radix">HEXRADIX</obj_property>
   </wvobject>
   <wvobject fp_name="/testbench/master_state" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">master_state[3:0]</obj_property>
      <obj_property name="ObjectShortName">master_state[3:0]</obj_property>
      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
   </wvobject>
   <wvobject fp_name="/testbench/wren_s" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">wren_s</obj_property>
      <obj_property name="ObjectShortName">wren_s</obj_property>
   </wvobject>
   <wvobject fp_name="/testbench/wr_ack_s" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">wr_ack_s</obj_property>
      <obj_property name="ObjectShortName">wr_ack_s</obj_property>
   </wvobject>
   <wvobject fp_name="/testbench/di_req_s" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">di_req_s</obj_property>
      <obj_property name="ObjectShortName">di_req_s</obj_property>
   </wvobject>
   <wvobject fp_name="/testbench/do_valid_s" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">do_valid_s</obj_property>
      <obj_property name="ObjectShortName">do_valid_s</obj_property>
   </wvobject>
   <wvobject fp_name="/testbench/s_do_reg" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">s_do_reg[7:0]</obj_property>
      <obj_property name="ObjectShortName">s_do_reg[7:0]</obj_property>
      <obj_property name="Radix">HEXRADIX</obj_property>
   </wvobject>
   <wvobject fp_name="/testbench/leds" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">leds[7:0]</obj_property>
      <obj_property name="ObjectShortName">leds[7:0]</obj_property>
      <obj_property name="Radix">HEXRADIX</obj_property>
   </wvobject>
   <wvobject fp_name="/testbench/slave_state" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">slave_state[3:0]</obj_property>
      <obj_property name="ObjectShortName">slave_state[3:0]</obj_property>
      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
   </wvobject>
</wave_config>

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