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[/] [vivado/] [steel-core.sim/] [sim_1/] [behav/] [xsim/] [tb_soc_top_vlog.prj] - Rev 11

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# compile verilog/system verilog design source files
verilog xil_defaultlib  \
"../../../../../rtl/alu.v" \
"../../../../../rtl/branch_unit.v" \
"../../../../../soc/bus_arbiter.v" \
"../../../../../rtl/csr_file.v" \
"../../../../../rtl/decoder.v" \
"../../../../../rtl/imm_generator.v" \
"../../../../../rtl/integer_file.v" \
"../../../../../rtl/load_unit.v" \
"../../../../../rtl/machine_control.v" \
"../../../../../soc/ram.v" \
"../../../../../soc/soc_top.v" \
"../../../../../rtl/steel_top.v" \
"../../../../../rtl/store_unit.v" \
"../../../../../soc/uart_tx.v" \
"../../../../../soc/bench/tb_soc_top.v" \

# compile glbl module
verilog xil_defaultlib "glbl.v"

# Do not sort compile order
nosort

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