OpenCores
URL https://opencores.org/ocsvn/steelcore/steelcore/trunk

Subversion Repositories steelcore

[/] [vivado/] [steel-core.sim/] [sim_1/] [behav/] [xsim/] [xvlog.log] - Rev 11

Compare with Previous | Blame | View Log

INFO: [VRFC 10-2263] Analyzing Verilog file "/home/rafa/ufrgs/steel-core/rtl/alu.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module alu
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/rafa/ufrgs/steel-core/rtl/branch_unit.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module branch_unit
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/rafa/ufrgs/steel-core/rtl/csr_file.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module csr_file
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/rafa/ufrgs/steel-core/rtl/decoder.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module decoder
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/rafa/ufrgs/steel-core/rtl/imm_generator.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module imm_generator
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/rafa/ufrgs/steel-core/rtl/integer_file.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module integer_file
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/rafa/ufrgs/steel-core/rtl/load_unit.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module load_unit
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/rafa/ufrgs/steel-core/rtl/machine_control.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module machine_control
INFO: [VRFC 10-2458] undeclared symbol FUNCT7_wfi, assumed default net type wire [/home/rafa/ufrgs/steel-core/rtl/machine_control.v:136]
INFO: [VRFC 10-2458] undeclared symbol RS2_ADDR_wfi, assumed default net type wire [/home/rafa/ufrgs/steel-core/rtl/machine_control.v:141]
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/rafa/ufrgs/steel-core/rtl/steel_top.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module steel_top
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/rafa/ufrgs/steel-core/rtl/store_unit.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module store_unit
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/rafa/ufrgs/steel-core/rtl/bench/tb_compliance.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_compliance

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.