OpenCores

URL https://opencores.org/ocsvn/systemverilog-uart16550/systemverilog-uart16550/trunk

Subversion Repositories systemverilog-uart16550

[/] [systemverilog-uart16550/] [trunk/] [sim/] [README_sim.txt] - Rev 3

Compare with Previous | Blame | View Log


 ** run simulation **  by hiroshi

Environment  : unix or cygwin

* align 4byte versoin

    make clean
    make work
    make align=ALIGN_4B

* align 1byte versoin

    make clean
    make work
    make align=ALIGN_1B

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.