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[/] [udp_ip_stack/] [trunk/] [rtl/] [vhdl/] [ipcores/] [xilinx/] [mac_layer_v2_1.xco] - Rev 15

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##############################################################
#
# Xilinx Core Generator version 13.2
# Date: Sat Jul 23 13:38:01 2011
#
##############################################################
#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
#  Generated from component: xilinx.com:ip:v6_emac:2.1
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6vlx240t
SET devicefamily = virtex6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ff1156
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -1
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Virtex-6_Embedded_Tri-Mode_Ethernet_MAC_Wrapper family Xilinx,_Inc. 2.1
# END Select
# BEGIN Parameters
CSET address_filter=false
CSET address_filter_enable=false
CSET axi_ipif=true
CSET client_side_data_width=8_bit
CSET clock_enable=true
CSET component_name=emac1
CSET management_interface=false
CSET mdio=false
CSET number_of_address_table_entries=0
CSET phy_an_enable=false
CSET phy_ignore_adzero=false
CSET phy_isolate=false
CSET phy_link_timer_value=13D
CSET phy_loopback_in_gtp=false
CSET phy_loopback_msb=false
CSET phy_powerdown=false
CSET phy_reset=false
CSET phy_unidirection_enable=false
CSET physical_interface=GMII
CSET rx_ctrl_lencheck_disable=false
CSET rx_disable_length=false
CSET rx_enable=true
CSET rx_flow_control_enable=false
CSET rx_half_duplex_enable=false
CSET rx_in_band_fcs_enable=false
CSET rx_jumbo_frame_enable=false
CSET rx_reset=false
CSET rx_vlan_enable=false
CSET serial_mode_switch_enable=false
CSET sgmii_mode=No_clock
CSET speed=1000_Mbps
CSET statistics_counters=false
CSET statistics_reset=true
CSET statistics_width=32bit
CSET tx_enable=true
CSET tx_flow_control_enable=false
CSET tx_half_duplex_enable=false
CSET tx_ifg_adjust_enable=false
CSET tx_in_band_fcs_enable=false
CSET tx_jumbo_frame_enable=false
CSET tx_reset=false
CSET tx_vlan_enable=false
CSET unicast_pause_mac_address_1=AA
CSET unicast_pause_mac_address_2=BB
CSET unicast_pause_mac_address_3=CC
CSET unicast_pause_mac_address_4=DD
CSET unicast_pause_mac_address_5=EE
CSET unicast_pause_mac_address_6=FF
# END Parameters
GENERATE
# CRC: fd590560

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