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[/] [udp_ip_stack/] [trunk/] [rtl/] [vhdl/] [ml605/] [udp_constraints.ucf] - Rev 4

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CONFIG PART = xc6vlx240tff1156-1;


########## ML605 Board ##########
NET  clk_in_p        LOC = J9   |IOSTANDARD = LVDS_25  |DIFF_TERM = TRUE;
NET  clk_in_n        LOC = H9   |IOSTANDARD = LVDS_25  |DIFF_TERM = TRUE;

Net reset         LOC = H10  |IOSTANDARD = LVCMOS15 |TIG;

# downgrade the Place:1153 error in the mapper
NET "reset" CLOCK_DEDICATED_ROUTE = FALSE;

#### Module LEDs_8Bit constraints
NET "display[0]" LOC = AC22;
NET "display[1]" LOC = AC24;
NET "display[2]" LOC = AE22;
NET "display[3]" LOC = AE23;
NET "display[4]" LOC = AB23;
NET "display[5]" LOC = AG23;
NET "display[6]" LOC = AE24;
NET "display[7]" LOC = AD24;

NET PBTX_LED            LOC = AD21;

#### Module Push_Buttons_4Bit constraints
NET PBTX                        LOC = H17;
NET reset_leds          LOC = G26;

#### Module DIP_Switches_4Bit constraints


Net phy_resetn       LOC = AH13 |IOSTANDARD = LVCMOS25 |TIG;

Net gmii_rxd<7>      LOC = AC13 |IOSTANDARD = LVCMOS25;
Net gmii_rxd<6>      LOC = AC12 |IOSTANDARD = LVCMOS25;
Net gmii_rxd<5>      LOC = AD11 |IOSTANDARD = LVCMOS25;
Net gmii_rxd<4>      LOC = AM12 |IOSTANDARD = LVCMOS25;
Net gmii_rxd<3>      LOC = AN12 |IOSTANDARD = LVCMOS25;
Net gmii_rxd<2>      LOC = AE14 |IOSTANDARD = LVCMOS25;
Net gmii_rxd<1>      LOC = AF14 |IOSTANDARD = LVCMOS25;
Net gmii_rxd<0>      LOC = AN13 |IOSTANDARD = LVCMOS25;

Net gmii_txd<7>      LOC = AF11 |IOSTANDARD = LVCMOS25;
Net gmii_txd<6>      LOC = AE11 |IOSTANDARD = LVCMOS25;
Net gmii_txd<5>      LOC = AM10 |IOSTANDARD = LVCMOS25;
Net gmii_txd<4>      LOC = AL10 |IOSTANDARD = LVCMOS25;
Net gmii_txd<3>      LOC = AG11 |IOSTANDARD = LVCMOS25;
Net gmii_txd<2>      LOC = AG10 |IOSTANDARD = LVCMOS25;
Net gmii_txd<1>      LOC = AL11 |IOSTANDARD = LVCMOS25;
Net gmii_txd<0>      LOC = AM11 |IOSTANDARD = LVCMOS25;

Net gmii_col         LOC = AK13 |IOSTANDARD = LVCMOS25;
Net gmii_crs         LOC = AL13 |IOSTANDARD = LVCMOS25;
Net mii_tx_clk       LOC = AD12 |IOSTANDARD = LVCMOS25;

Net gmii_tx_en       LOC = AJ10 |IOSTANDARD = LVCMOS25;
Net gmii_tx_er       LOC = AH10 |IOSTANDARD = LVCMOS25;
Net gmii_tx_clk      LOC = AH12 |IOSTANDARD = LVCMOS25;

Net gmii_rx_dv       LOC = AM13 |IOSTANDARD = LVCMOS25;
Net gmii_rx_er       LOC = AG12 |IOSTANDARD = LVCMOS25;
# P20 - GCLK7 
Net gmii_rx_clk      LOC = AP11 |IOSTANDARD = LVCMOS25;



NET "clk_in_p" TNM_NET = "clk_in_p";
TIMESPEC "TS_emac1_clk_in_p" = PERIOD "clk_in_p" 5.000 ns HIGH 50% INPUT_JITTER 50.0ps;


# Ethernet GTX_CLK high quality 125 MHz reference clock
NET "*mac_block/gtx_clk_bufg" TNM_NET = "ref_gtx_clk";
TIMEGRP "emac1_clk_ref_gtx" = "ref_gtx_clk";
TIMESPEC TS_emac1_clk_ref_gtx = PERIOD "N/A" 8 ns HIGH 50%;


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