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URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [sim/] [rtl_sim/] [run/] [Makefile] - Rev 88

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VERILOG_FILES = ./../../../rtl/verilog/versatile_library.v

wb_b3_ram_be.v:
        vppreproc --noline --noblank +define+SYSTEMVERILOG +define+WB_B3_RAM_BE $(VERILOG_FILES) > wb_b3_ram_be.v

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