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[/] [vhdl_wb_tb/] [trunk/] [rtl/] [vhdl/] [packages/] [my_project_pkg.vhd] - Rev 2

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---------------------------------------------------------------------- 
----                                                              ---- 
----  WISHBONE XXX IP Core                                        ---- 
----                                                              ---- 
----  This file is part of the XXX project                        ---- 
----  http://www.opencores.org/cores/xxx/                         ---- 
----                                                              ---- 
----  Description                                                 ---- 
----  Implementation of XXX IP core according to                  ---- 
----  XXX IP core specification document.                         ---- 
----                                                              ---- 
----  To Do:                                                      ---- 
----   - Adjust and rename this package for your project          ---- 
----   - remove these comments                                    ---- 
----                                                              ---- 
----  Author(s):                                                  ---- 
----      - First & Last Name, email@opencores.org                ---- 
----                                                              ---- 
----------------------------------------------------------------------
--    SVN information
--
--      $URL:  $
-- $Revision:  $
--     $Date:  $
--   $Author:  $
--       $Id:  $
--
---------------------------------------------------------------------- 
----                                                              ---- 
---- Copyright (C) 2018 Authors and OPENCORES.ORG                 ---- 
----                                                              ---- 
---- This source file may be used and distributed without         ---- 
---- restriction provided that this copyright statement is not    ---- 
---- removed from the file and that any derivative work contains  ---- 
---- the original copyright notice and the associated disclaimer. ---- 
----                                                              ---- 
---- This source file is free software; you can redistribute it   ---- 
---- and/or modify it under the terms of the GNU Lesser General   ---- 
---- Public License as published by the Free Software Foundation; ---- 
---- either version 2.1 of the License, or (at your option) any   ---- 
---- later version.                                               ---- 
----                                                              ---- 
---- This source is distributed in the hope that it will be       ---- 
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
---- details.                                                     ---- 
----                                                              ---- 
---- You should have received a copy of the GNU Lesser General    ---- 
---- Public License along with this source; if not, download it   ---- 
---- from http://www.opencores.org/lgpl.shtml                     ---- 
----                                                              ---- 
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library work;
 
package my_project_pkg is
 
  constant wishbone_address_width_c : integer := 32;
  constant wishbone_data_width_c    : integer := 32;
  constant wishbone_data_of_unused_address_c : std_logic_vector(wishbone_data_width_c-1 DOWNTO 0) := X"DEADDEAD"; -- "X" might lead to less resources. Meaningful value might ease debugging
  constant wishbone_data_of_unused_address_p : std_logic_vector(wishbone_data_width_c-1 DOWNTO 0) := X"DEADBEEF"; -- "X" might lead to less resources. Meaningful value might ease debugging
 
  subtype wishbone_tag_data_t is std_logic_vector(1 downto 0);
  subtype wishbone_tag_address_t is std_logic_vector(1 downto 0);
  subtype wishbone_tag_cycle_t is std_logic_vector(1 downto 0);
 
  --type t_wishbone_interface_mode is (CLASSIC, PIPELINED);
  --type t_wishbone_address_granularity is (BYTE, WORD);
  constant zero_c : std_logic_vector(511 downto 0) := (others => '0');
end my_project_pkg;
 
package body my_project_pkg is
end my_project_pkg;
 
 

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