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[/] [z80soc/] [trunk/] [V0.7.3/] [DE2115/] [073DE2115d.sta.rpt] - Rev 46
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TimeQuest Timing Analyzer report for 073DE2115dFri Jun 17 12:51:07 2016Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition---------------------; Table of Contents ;---------------------1. Legal Notice2. TimeQuest Timing Analyzer Summary3. Parallel Compilation4. Clocks5. Fmax Summary6. Timing Closure Recommendations7. Setup Summary8. Hold Summary9. Recovery Summary10. Removal Summary11. Minimum Pulse Width Summary12. Setup: 'clk_div:clkdiv_inst|clock_100Hz'13. Setup: 'SW[15]'14. Setup: 'CLOCK_50'15. Setup: 'T80se:z80_inst|MREQ_n'16. Setup: 'clk_div:clkdiv_inst|clock_25MHz'17. Setup: 'ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered'18. Setup: 'clk_div:clkdiv_inst|clock_25Mhz_int'19. Setup: 'clk_div:clkdiv_inst|clock_1Mhz_int'20. Setup: 'clk_div:clkdiv_inst|clock_10Khz_int'21. Setup: 'clk_div:clkdiv_inst|clock_100Khz_int'22. Setup: 'clk_div:clkdiv_inst|clock_1Khz_int'23. Hold: 'SW[15]'24. Hold: 'clk_div:clkdiv_inst|clock_100Hz'25. Hold: 'T80se:z80_inst|MREQ_n'26. Hold: 'ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered'27. Hold: 'clk_div:clkdiv_inst|clock_1Mhz_int'28. Hold: 'CLOCK_50'29. Hold: 'clk_div:clkdiv_inst|clock_10Khz_int'30. Hold: 'clk_div:clkdiv_inst|clock_25MHz'31. Hold: 'clk_div:clkdiv_inst|clock_100Khz_int'32. Hold: 'clk_div:clkdiv_inst|clock_1Khz_int'33. Hold: 'clk_div:clkdiv_inst|clock_25Mhz_int'34. Recovery: 'ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set'35. Removal: 'ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set'36. Minimum Pulse Width: 'SW[15]'37. Minimum Pulse Width: 'CLOCK_50'38. Minimum Pulse Width: 'clk_div:clkdiv_inst|clock_100Hz'39. Minimum Pulse Width: 'clk_div:clkdiv_inst|clock_25MHz'40. Minimum Pulse Width: 'ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered'41. Minimum Pulse Width: 'clk_div:clkdiv_inst|clock_25Mhz_int'42. Minimum Pulse Width: 'clk_div:clkdiv_inst|clock_100Khz_int'43. Minimum Pulse Width: 'clk_div:clkdiv_inst|clock_10Khz_int'44. Minimum Pulse Width: 'clk_div:clkdiv_inst|clock_1Khz_int'45. Minimum Pulse Width: 'clk_div:clkdiv_inst|clock_1Mhz_int'46. Minimum Pulse Width: 'ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set'47. Minimum Pulse Width: 'T80se:z80_inst|MREQ_n'48. Setup Times49. Hold Times50. Clock to Output Times51. Minimum Clock to Output Times52. Output Enable Times53. Minimum Output Enable Times54. Output Disable Times55. Minimum Output Disable Times56. Metastability Report57. Board Trace Model Assignments58. Input Transition Times59. Signal Integrity Metrics (Slow 1200mv 85c Model)60. Setup Transfers61. Hold Transfers62. Recovery Transfers63. Removal Transfers64. Report TCCS65. Report RSKM66. Unconstrained Paths67. TimeQuest Timing Analyzer Messages----------------; Legal Notice ;----------------Copyright (C) 1991-2013 Altera CorporationYour use of Altera Corporation's design tools, logic functionsand other software and tools, and its AMPP partner logicfunctions, and any output files from any of the foregoing(including device programming or simulation files), and anyassociated documentation or information are expressly subjectto the terms and conditions of the Altera Program LicenseSubscription Agreement, Altera MegaCore Function LicenseAgreement, or other applicable license agreement, including,without limitation, that your use is for the sole purpose ofprogramming logic devices manufactured by Altera and sold byAltera or its authorized distributors. Please refer to theapplicable agreement for further details.+----------------------------------------------------------------------------------------+; TimeQuest Timing Analyzer Summary ;+--------------------+-------------------------------------------------------------------+; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;; Revision Name ; 073DE2115d ;; Device Family ; Cyclone IV E ;; Device Name ; EP4CE115F29C7 ;; Timing Models ; Final ;; Delay Model ; Slow 1200mV 85C Model ;; Rise/Fall Delays ; Enabled ;+--------------------+-------------------------------------------------------------------+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.+-------------------------------------+; Parallel Compilation ;+----------------------------+--------+; Processors ; Number ;+----------------------------+--------+; Number detected on machine ; 2 ;; Maximum allowed ; 1 ;+----------------------------+--------++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Clocks ;+-------------------------------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------------------------------+; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;+-------------------------------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------------------------------+; clk_div:clkdiv_inst|clock_1Khz_int ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { clk_div:clkdiv_inst|clock_1Khz_int } ;; clk_div:clkdiv_inst|clock_1Mhz_int ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { clk_div:clkdiv_inst|clock_1Mhz_int } ;; clk_div:clkdiv_inst|clock_10Khz_int ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { clk_div:clkdiv_inst|clock_10Khz_int } ;; clk_div:clkdiv_inst|clock_25MHz ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { clk_div:clkdiv_inst|clock_25MHz } ;; clk_div:clkdiv_inst|clock_25Mhz_int ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { clk_div:clkdiv_inst|clock_25Mhz_int } ;; clk_div:clkdiv_inst|clock_100Hz ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { clk_div:clkdiv_inst|clock_100Hz } ;; clk_div:clkdiv_inst|clock_100Khz_int ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { clk_div:clkdiv_inst|clock_100Khz_int } ;; CLOCK_50 ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { CLOCK_50 } ;; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered } ;; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set } ;; SW[15] ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { SW[15] } ;; T80se:z80_inst|MREQ_n ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { T80se:z80_inst|MREQ_n } ;+-------------------------------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------+; Fmax Summary ;+------------+-----------------+-------------------------------------------------------------+------------------------------------------------+; Fmax ; Restricted Fmax ; Clock Name ; Note ;+------------+-----------------+-------------------------------------------------------------+------------------------------------------------+; 61.46 MHz ; 61.46 MHz ; SW[15] ; ;; 64.28 MHz ; 64.28 MHz ; clk_div:clkdiv_inst|clock_100Hz ; ;; 147.91 MHz ; 147.91 MHz ; clk_div:clkdiv_inst|clock_25MHz ; ;; 245.82 MHz ; 245.82 MHz ; CLOCK_50 ; ;; 323.62 MHz ; 323.62 MHz ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ;; 527.7 MHz ; 437.64 MHz ; clk_div:clkdiv_inst|clock_25Mhz_int ; limit due to minimum period restriction (tmin) ;; 600.6 MHz ; 437.64 MHz ; clk_div:clkdiv_inst|clock_1Mhz_int ; limit due to minimum period restriction (tmin) ;; 657.03 MHz ; 437.64 MHz ; clk_div:clkdiv_inst|clock_10Khz_int ; limit due to minimum period restriction (tmin) ;; 664.01 MHz ; 437.64 MHz ; clk_div:clkdiv_inst|clock_100Khz_int ; limit due to minimum period restriction (tmin) ;; 757.58 MHz ; 437.64 MHz ; clk_div:clkdiv_inst|clock_1Khz_int ; limit due to minimum period restriction (tmin) ;+------------+-----------------+-------------------------------------------------------------+------------------------------------------------+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.----------------------------------; Timing Closure Recommendations ;----------------------------------HTML report is unavailable in plain text report export.+---------------------------------------------------------------------------------------+; Setup Summary ;+-------------------------------------------------------------+---------+---------------+; Clock ; Slack ; End Point TNS ;+-------------------------------------------------------------+---------+---------------+; clk_div:clkdiv_inst|clock_100Hz ; -18.853 ; -6188.176 ;; SW[15] ; -15.271 ; -4622.675 ;; CLOCK_50 ; -9.393 ; -279.199 ;; T80se:z80_inst|MREQ_n ; -6.449 ; -1219.866 ;; clk_div:clkdiv_inst|clock_25MHz ; -5.761 ; -272.854 ;; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; -2.090 ; -36.933 ;; clk_div:clkdiv_inst|clock_25Mhz_int ; -0.895 ; -3.964 ;; clk_div:clkdiv_inst|clock_1Mhz_int ; -0.665 ; -0.945 ;; clk_div:clkdiv_inst|clock_10Khz_int ; -0.522 ; -0.875 ;; clk_div:clkdiv_inst|clock_100Khz_int ; -0.506 ; -0.831 ;; clk_div:clkdiv_inst|clock_1Khz_int ; -0.320 ; -0.600 ;+-------------------------------------------------------------+---------+---------------++--------------------------------------------------------------------------------------+; Hold Summary ;+-------------------------------------------------------------+--------+---------------+; Clock ; Slack ; End Point TNS ;+-------------------------------------------------------------+--------+---------------+; SW[15] ; -5.753 ; -586.538 ;; clk_div:clkdiv_inst|clock_100Hz ; -1.638 ; -15.071 ;; T80se:z80_inst|MREQ_n ; -1.628 ; -63.193 ;; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; -0.418 ; -0.418 ;; clk_div:clkdiv_inst|clock_1Mhz_int ; -0.319 ; -0.319 ;; CLOCK_50 ; -0.260 ; -0.703 ;; clk_div:clkdiv_inst|clock_10Khz_int ; -0.127 ; -0.127 ;; clk_div:clkdiv_inst|clock_25MHz ; 0.048 ; 0.000 ;; clk_div:clkdiv_inst|clock_100Khz_int ; 0.106 ; 0.000 ;; clk_div:clkdiv_inst|clock_1Khz_int ; 0.440 ; 0.000 ;; clk_div:clkdiv_inst|clock_25Mhz_int ; 0.477 ; 0.000 ;+-------------------------------------------------------------+--------+---------------++--------------------------------------------------------------------------+; Recovery Summary ;+-------------------------------------------------+--------+---------------+; Clock ; Slack ; End Point TNS ;+-------------------------------------------------+--------+---------------+; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set ; -2.384 ; -2.384 ;+-------------------------------------------------+--------+---------------++-------------------------------------------------------------------------+; Removal Summary ;+-------------------------------------------------+-------+---------------+; Clock ; Slack ; End Point TNS ;+-------------------------------------------------+-------+---------------+; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set ; 2.874 ; 0.000 ;+-------------------------------------------------+-------+---------------++--------------------------------------------------------------------------------------+; Minimum Pulse Width Summary ;+-------------------------------------------------------------+--------+---------------+; Clock ; Slack ; End Point TNS ;+-------------------------------------------------------------+--------+---------------+; SW[15] ; -3.000 ; -1318.219 ;; CLOCK_50 ; -3.000 ; -143.065 ;; clk_div:clkdiv_inst|clock_100Hz ; -2.693 ; -619.205 ;; clk_div:clkdiv_inst|clock_25MHz ; -2.693 ; -178.641 ;; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; -1.285 ; -29.555 ;; clk_div:clkdiv_inst|clock_25Mhz_int ; -1.285 ; -7.710 ;; clk_div:clkdiv_inst|clock_100Khz_int ; -1.285 ; -5.140 ;; clk_div:clkdiv_inst|clock_10Khz_int ; -1.285 ; -5.140 ;; clk_div:clkdiv_inst|clock_1Khz_int ; -1.285 ; -5.140 ;; clk_div:clkdiv_inst|clock_1Mhz_int ; -1.285 ; -5.140 ;; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set ; -1.285 ; -1.285 ;; T80se:z80_inst|MREQ_n ; 0.261 ; 0.000 ;+-------------------------------------------------------------+--------+---------------++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Setup: 'clk_div:clkdiv_inst|clock_100Hz' ;+---------+---------------------------------+------------------------------------------------+--------------+---------------------------------+--------------+------------+------------+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;+---------+---------------------------------+------------------------------------------------+--------------+---------------------------------+--------------+------------+------------+; -18.853 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[5][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.362 ; 15.479 ;; -18.853 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[6][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.362 ; 15.479 ;; -18.778 ; T80se:z80_inst|T80:u0|F[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[5][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.363 ; 15.403 ;; -18.778 ; T80se:z80_inst|T80:u0|F[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[6][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.363 ; 15.403 ;; -18.756 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[3][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.357 ; 15.387 ;; -18.754 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[7][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.358 ; 15.384 ;; -18.754 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[4][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.358 ; 15.384 ;; -18.682 ; T80se:z80_inst|T80:u0|F[6] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[5][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.364 ; 15.306 ;; -18.682 ; T80se:z80_inst|T80:u0|F[6] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[6][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.364 ; 15.306 ;; -18.681 ; T80se:z80_inst|T80:u0|F[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[3][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.358 ; 15.311 ;; -18.679 ; T80se:z80_inst|T80:u0|F[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[7][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.359 ; 15.308 ;; -18.679 ; T80se:z80_inst|T80:u0|F[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[4][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.359 ; 15.308 ;; -18.650 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[1][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.359 ; 15.279 ;; -18.589 ; T80se:z80_inst|T80:u0|IR[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[5][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.362 ; 15.215 ;; -18.589 ; T80se:z80_inst|T80:u0|IR[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[6][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.362 ; 15.215 ;; -18.585 ; T80se:z80_inst|T80:u0|F[6] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[3][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.359 ; 15.214 ;; -18.583 ; T80se:z80_inst|T80:u0|F[6] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[7][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.360 ; 15.211 ;; -18.583 ; T80se:z80_inst|T80:u0|F[6] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[4][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.360 ; 15.211 ;; -18.575 ; T80se:z80_inst|T80:u0|F[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[1][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.360 ; 15.203 ;; -18.568 ; T80se:z80_inst|T80:u0|F[7] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[5][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.364 ; 15.192 ;; -18.568 ; T80se:z80_inst|T80:u0|F[7] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[6][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.364 ; 15.192 ;; -18.492 ; T80se:z80_inst|T80:u0|MCycle[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[5][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.362 ; 15.118 ;; -18.492 ; T80se:z80_inst|T80:u0|MCycle[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[6][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.362 ; 15.118 ;; -18.492 ; T80se:z80_inst|T80:u0|IR[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[3][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.357 ; 15.123 ;; -18.490 ; T80se:z80_inst|T80:u0|IR[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[7][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.358 ; 15.120 ;; -18.490 ; T80se:z80_inst|T80:u0|IR[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[4][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.358 ; 15.120 ;; -18.489 ; T80se:z80_inst|T80:u0|IR[3] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[5][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.363 ; 15.114 ;; -18.489 ; T80se:z80_inst|T80:u0|IR[3] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[6][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.363 ; 15.114 ;; -18.480 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|IncDecZ ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.366 ; 15.102 ;; -18.479 ; T80se:z80_inst|T80:u0|F[6] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[1][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.361 ; 15.106 ;; -18.471 ; T80se:z80_inst|T80:u0|F[7] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[3][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.359 ; 15.100 ;; -18.469 ; T80se:z80_inst|T80:u0|F[7] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[7][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.360 ; 15.097 ;; -18.469 ; T80se:z80_inst|T80:u0|F[7] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[4][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.360 ; 15.097 ;; -18.416 ; T80se:z80_inst|T80:u0|IR[1] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[5][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.362 ; 15.042 ;; -18.416 ; T80se:z80_inst|T80:u0|IR[1] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[6][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.362 ; 15.042 ;; -18.410 ; T80se:z80_inst|T80:u0|IR[6] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[5][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.362 ; 15.036 ;; -18.410 ; T80se:z80_inst|T80:u0|IR[6] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[6][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.362 ; 15.036 ;; -18.405 ; T80se:z80_inst|T80:u0|F[0] ; T80se:z80_inst|T80:u0|IncDecZ ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.367 ; 15.026 ;; -18.395 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[7][1] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.359 ; 15.024 ;; -18.395 ; T80se:z80_inst|T80:u0|MCycle[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[3][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.357 ; 15.026 ;; -18.394 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[5][1] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.359 ; 15.023 ;; -18.393 ; T80se:z80_inst|T80:u0|MCycle[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[7][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.358 ; 15.023 ;; -18.393 ; T80se:z80_inst|T80:u0|MCycle[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[4][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.358 ; 15.023 ;; -18.392 ; T80se:z80_inst|T80:u0|IR[3] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[3][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.358 ; 15.022 ;; -18.390 ; T80se:z80_inst|T80:u0|IR[3] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[7][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.359 ; 15.019 ;; -18.390 ; T80se:z80_inst|T80:u0|IR[3] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[4][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.359 ; 15.019 ;; -18.386 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[6][1] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.357 ; 15.017 ;; -18.386 ; T80se:z80_inst|T80:u0|IR[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[1][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.359 ; 15.015 ;; -18.384 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[4][1] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.357 ; 15.015 ;; -18.381 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[1][3] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.360 ; 15.009 ;; -18.379 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[2][3] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.360 ; 15.007 ;; -18.365 ; T80se:z80_inst|T80:u0|F[7] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[1][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.361 ; 14.992 ;; -18.357 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[7][7] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.356 ; 14.989 ;; -18.320 ; T80se:z80_inst|T80:u0|F[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[7][1] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.360 ; 14.948 ;; -18.319 ; T80se:z80_inst|T80:u0|F[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[5][1] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.360 ; 14.947 ;; -18.319 ; T80se:z80_inst|T80:u0|IR[1] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[3][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.357 ; 14.950 ;; -18.317 ; T80se:z80_inst|T80:u0|IR[1] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[7][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.358 ; 14.947 ;; -18.317 ; T80se:z80_inst|T80:u0|IR[1] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[4][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.358 ; 14.947 ;; -18.313 ; T80se:z80_inst|T80:u0|IR[6] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[3][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.357 ; 14.944 ;; -18.311 ; T80se:z80_inst|T80:u0|IR[6] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[7][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.358 ; 14.941 ;; -18.311 ; T80se:z80_inst|T80:u0|IR[6] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[4][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.358 ; 14.941 ;; -18.311 ; T80se:z80_inst|T80:u0|F[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[6][1] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.358 ; 14.941 ;; -18.309 ; T80se:z80_inst|T80:u0|F[6] ; T80se:z80_inst|T80:u0|IncDecZ ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.368 ; 14.929 ;; -18.309 ; T80se:z80_inst|T80:u0|F[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[4][1] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.358 ; 14.939 ;; -18.306 ; T80se:z80_inst|T80:u0|F[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[1][3] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.361 ; 14.933 ;; -18.304 ; T80se:z80_inst|T80:u0|F[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[2][3] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.361 ; 14.931 ;; -18.289 ; T80se:z80_inst|T80:u0|MCycle[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[1][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.359 ; 14.918 ;; -18.286 ; T80se:z80_inst|T80:u0|IR[3] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[1][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.360 ; 14.914 ;; -18.282 ; T80se:z80_inst|T80:u0|F[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[7][7] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.357 ; 14.913 ;; -18.229 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[0][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.359 ; 14.858 ;; -18.227 ; T80se:z80_inst|T80:u0|MCycle[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[5][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.362 ; 14.853 ;; -18.227 ; T80se:z80_inst|T80:u0|MCycle[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[6][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.362 ; 14.853 ;; -18.224 ; T80se:z80_inst|T80:u0|F[6] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[7][1] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.361 ; 14.851 ;; -18.223 ; T80se:z80_inst|T80:u0|F[6] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[5][1] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.361 ; 14.850 ;; -18.216 ; T80se:z80_inst|T80:u0|IR[2] ; T80se:z80_inst|T80:u0|IncDecZ ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.366 ; 14.838 ;; -18.215 ; T80se:z80_inst|T80:u0|F[6] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[6][1] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.359 ; 14.844 ;; -18.213 ; T80se:z80_inst|T80:u0|F[6] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[4][1] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.359 ; 14.842 ;; -18.213 ; T80se:z80_inst|T80:u0|IR[1] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[1][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.359 ; 14.842 ;; -18.210 ; T80se:z80_inst|T80:u0|F[6] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[1][3] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.362 ; 14.836 ;; -18.208 ; T80se:z80_inst|T80:u0|F[6] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[2][3] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.362 ; 14.834 ;; -18.207 ; T80se:z80_inst|T80:u0|IR[6] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[1][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.359 ; 14.836 ;; -18.195 ; T80se:z80_inst|T80:u0|F[7] ; T80se:z80_inst|T80:u0|IncDecZ ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.368 ; 14.815 ;; -18.193 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[5][3] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.357 ; 14.824 ;; -18.192 ; T80se:z80_inst|T80:u0|IR[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[5][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.362 ; 14.818 ;; -18.192 ; T80se:z80_inst|T80:u0|IR[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[6][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.362 ; 14.818 ;; -18.190 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[7][3] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.357 ; 14.821 ;; -18.186 ; T80se:z80_inst|T80:u0|F[6] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[7][7] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.358 ; 14.816 ;; -18.178 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[5][7] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.357 ; 14.809 ;; -18.177 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[7][7] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.357 ; 14.808 ;; -18.158 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[6][4] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.357 ; 14.789 ;; -18.158 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[4][4] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.357 ; 14.789 ;; -18.154 ; T80se:z80_inst|T80:u0|F[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[0][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.360 ; 14.782 ;; -18.153 ; T80se:z80_inst|T80:u0|MCycle[1] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[5][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.362 ; 14.779 ;; -18.153 ; T80se:z80_inst|T80:u0|MCycle[1] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[6][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.362 ; 14.779 ;; -18.143 ; T80se:z80_inst|T80:u0|IR[4] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[5][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.363 ; 14.768 ;; -18.143 ; T80se:z80_inst|T80:u0|IR[4] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[6][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.363 ; 14.768 ;; -18.134 ; T80se:z80_inst|T80:u0|IR[7] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[5][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.351 ; 14.771 ;; -18.134 ; T80se:z80_inst|T80:u0|IR[7] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[6][6] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.351 ; 14.771 ;; -18.131 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[3][3] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.359 ; 14.760 ;; -18.131 ; T80se:z80_inst|T80:u0|IR[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[7][1] ; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 1.000 ; -4.359 ; 14.760 ;+---------+---------------------------------+------------------------------------------------+--------------+---------------------------------+--------------+------------+------------++------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Setup: 'SW[15]' ;+---------+---------------------------------+------------------------------------------------+--------------+-------------+--------------+------------+------------+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;+---------+---------------------------------+------------------------------------------------+--------------+-------------+--------------+------------+------------+; -15.271 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[5][6] ; SW[15] ; SW[15] ; 1.000 ; -0.790 ; 15.479 ;; -15.271 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[6][6] ; SW[15] ; SW[15] ; 1.000 ; -0.790 ; 15.479 ;; -15.196 ; T80se:z80_inst|T80:u0|F[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[5][6] ; SW[15] ; SW[15] ; 1.000 ; -0.791 ; 15.403 ;; -15.196 ; T80se:z80_inst|T80:u0|F[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[6][6] ; SW[15] ; SW[15] ; 1.000 ; -0.791 ; 15.403 ;; -15.174 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[3][6] ; SW[15] ; SW[15] ; 1.000 ; -0.785 ; 15.387 ;; -15.172 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[7][6] ; SW[15] ; SW[15] ; 1.000 ; -0.786 ; 15.384 ;; -15.172 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[4][6] ; SW[15] ; SW[15] ; 1.000 ; -0.786 ; 15.384 ;; -15.100 ; T80se:z80_inst|T80:u0|F[6] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[5][6] ; SW[15] ; SW[15] ; 1.000 ; -0.792 ; 15.306 ;; -15.100 ; T80se:z80_inst|T80:u0|F[6] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[6][6] ; SW[15] ; SW[15] ; 1.000 ; -0.792 ; 15.306 ;; -15.099 ; T80se:z80_inst|T80:u0|F[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[3][6] ; SW[15] ; SW[15] ; 1.000 ; -0.786 ; 15.311 ;; -15.097 ; T80se:z80_inst|T80:u0|F[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[7][6] ; SW[15] ; SW[15] ; 1.000 ; -0.787 ; 15.308 ;; -15.097 ; T80se:z80_inst|T80:u0|F[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[4][6] ; SW[15] ; SW[15] ; 1.000 ; -0.787 ; 15.308 ;; -15.068 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[1][6] ; SW[15] ; SW[15] ; 1.000 ; -0.787 ; 15.279 ;; -15.031 ; T80se:z80_inst|T80:u0|IR[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[5][6] ; SW[15] ; SW[15] ; 1.000 ; -0.814 ; 15.215 ;; -15.031 ; T80se:z80_inst|T80:u0|IR[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[6][6] ; SW[15] ; SW[15] ; 1.000 ; -0.814 ; 15.215 ;; -15.003 ; T80se:z80_inst|T80:u0|F[6] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[3][6] ; SW[15] ; SW[15] ; 1.000 ; -0.787 ; 15.214 ;; -15.001 ; T80se:z80_inst|T80:u0|F[6] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[7][6] ; SW[15] ; SW[15] ; 1.000 ; -0.788 ; 15.211 ;; -15.001 ; T80se:z80_inst|T80:u0|F[6] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[4][6] ; SW[15] ; SW[15] ; 1.000 ; -0.788 ; 15.211 ;; -14.993 ; T80se:z80_inst|T80:u0|F[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[1][6] ; SW[15] ; SW[15] ; 1.000 ; -0.788 ; 15.203 ;; -14.986 ; T80se:z80_inst|T80:u0|F[7] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[5][6] ; SW[15] ; SW[15] ; 1.000 ; -0.792 ; 15.192 ;; -14.986 ; T80se:z80_inst|T80:u0|F[7] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[6][6] ; SW[15] ; SW[15] ; 1.000 ; -0.792 ; 15.192 ;; -14.934 ; T80se:z80_inst|T80:u0|IR[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[3][6] ; SW[15] ; SW[15] ; 1.000 ; -0.809 ; 15.123 ;; -14.934 ; T80se:z80_inst|T80:u0|MCycle[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[5][6] ; SW[15] ; SW[15] ; 1.000 ; -0.814 ; 15.118 ;; -14.934 ; T80se:z80_inst|T80:u0|MCycle[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[6][6] ; SW[15] ; SW[15] ; 1.000 ; -0.814 ; 15.118 ;; -14.932 ; T80se:z80_inst|T80:u0|IR[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[7][6] ; SW[15] ; SW[15] ; 1.000 ; -0.810 ; 15.120 ;; -14.932 ; T80se:z80_inst|T80:u0|IR[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[4][6] ; SW[15] ; SW[15] ; 1.000 ; -0.810 ; 15.120 ;; -14.931 ; T80se:z80_inst|T80:u0|IR[3] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[5][6] ; SW[15] ; SW[15] ; 1.000 ; -0.815 ; 15.114 ;; -14.931 ; T80se:z80_inst|T80:u0|IR[3] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[6][6] ; SW[15] ; SW[15] ; 1.000 ; -0.815 ; 15.114 ;; -14.898 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|IncDecZ ; SW[15] ; SW[15] ; 1.000 ; -0.794 ; 15.102 ;; -14.897 ; T80se:z80_inst|T80:u0|F[6] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[1][6] ; SW[15] ; SW[15] ; 1.000 ; -0.789 ; 15.106 ;; -14.889 ; T80se:z80_inst|T80:u0|F[7] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[3][6] ; SW[15] ; SW[15] ; 1.000 ; -0.787 ; 15.100 ;; -14.887 ; T80se:z80_inst|T80:u0|F[7] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[7][6] ; SW[15] ; SW[15] ; 1.000 ; -0.788 ; 15.097 ;; -14.887 ; T80se:z80_inst|T80:u0|F[7] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[4][6] ; SW[15] ; SW[15] ; 1.000 ; -0.788 ; 15.097 ;; -14.858 ; T80se:z80_inst|T80:u0|IR[1] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[5][6] ; SW[15] ; SW[15] ; 1.000 ; -0.814 ; 15.042 ;; -14.858 ; T80se:z80_inst|T80:u0|IR[1] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[6][6] ; SW[15] ; SW[15] ; 1.000 ; -0.814 ; 15.042 ;; -14.852 ; T80se:z80_inst|T80:u0|IR[6] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[5][6] ; SW[15] ; SW[15] ; 1.000 ; -0.814 ; 15.036 ;; -14.852 ; T80se:z80_inst|T80:u0|IR[6] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[6][6] ; SW[15] ; SW[15] ; 1.000 ; -0.814 ; 15.036 ;; -14.837 ; T80se:z80_inst|T80:u0|MCycle[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[3][6] ; SW[15] ; SW[15] ; 1.000 ; -0.809 ; 15.026 ;; -14.835 ; T80se:z80_inst|T80:u0|MCycle[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[7][6] ; SW[15] ; SW[15] ; 1.000 ; -0.810 ; 15.023 ;; -14.835 ; T80se:z80_inst|T80:u0|MCycle[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[4][6] ; SW[15] ; SW[15] ; 1.000 ; -0.810 ; 15.023 ;; -14.834 ; T80se:z80_inst|T80:u0|IR[3] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[3][6] ; SW[15] ; SW[15] ; 1.000 ; -0.810 ; 15.022 ;; -14.832 ; T80se:z80_inst|T80:u0|IR[3] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[7][6] ; SW[15] ; SW[15] ; 1.000 ; -0.811 ; 15.019 ;; -14.832 ; T80se:z80_inst|T80:u0|IR[3] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[4][6] ; SW[15] ; SW[15] ; 1.000 ; -0.811 ; 15.019 ;; -14.828 ; T80se:z80_inst|T80:u0|IR[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[1][6] ; SW[15] ; SW[15] ; 1.000 ; -0.811 ; 15.015 ;; -14.823 ; T80se:z80_inst|T80:u0|F[0] ; T80se:z80_inst|T80:u0|IncDecZ ; SW[15] ; SW[15] ; 1.000 ; -0.795 ; 15.026 ;; -14.813 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[7][1] ; SW[15] ; SW[15] ; 1.000 ; -0.787 ; 15.024 ;; -14.812 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[5][1] ; SW[15] ; SW[15] ; 1.000 ; -0.787 ; 15.023 ;; -14.804 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[6][1] ; SW[15] ; SW[15] ; 1.000 ; -0.785 ; 15.017 ;; -14.802 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[4][1] ; SW[15] ; SW[15] ; 1.000 ; -0.785 ; 15.015 ;; -14.799 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[1][3] ; SW[15] ; SW[15] ; 1.000 ; -0.788 ; 15.009 ;; -14.797 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[2][3] ; SW[15] ; SW[15] ; 1.000 ; -0.788 ; 15.007 ;; -14.783 ; T80se:z80_inst|T80:u0|F[7] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[1][6] ; SW[15] ; SW[15] ; 1.000 ; -0.789 ; 14.992 ;; -14.775 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[7][7] ; SW[15] ; SW[15] ; 1.000 ; -0.784 ; 14.989 ;; -14.761 ; T80se:z80_inst|T80:u0|IR[1] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[3][6] ; SW[15] ; SW[15] ; 1.000 ; -0.809 ; 14.950 ;; -14.759 ; T80se:z80_inst|T80:u0|IR[1] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[7][6] ; SW[15] ; SW[15] ; 1.000 ; -0.810 ; 14.947 ;; -14.759 ; T80se:z80_inst|T80:u0|IR[1] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[4][6] ; SW[15] ; SW[15] ; 1.000 ; -0.810 ; 14.947 ;; -14.755 ; T80se:z80_inst|T80:u0|IR[6] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[3][6] ; SW[15] ; SW[15] ; 1.000 ; -0.809 ; 14.944 ;; -14.753 ; T80se:z80_inst|T80:u0|IR[6] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[7][6] ; SW[15] ; SW[15] ; 1.000 ; -0.810 ; 14.941 ;; -14.753 ; T80se:z80_inst|T80:u0|IR[6] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[4][6] ; SW[15] ; SW[15] ; 1.000 ; -0.810 ; 14.941 ;; -14.738 ; T80se:z80_inst|T80:u0|F[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[7][1] ; SW[15] ; SW[15] ; 1.000 ; -0.788 ; 14.948 ;; -14.737 ; T80se:z80_inst|T80:u0|F[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[5][1] ; SW[15] ; SW[15] ; 1.000 ; -0.788 ; 14.947 ;; -14.731 ; T80se:z80_inst|T80:u0|MCycle[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[1][6] ; SW[15] ; SW[15] ; 1.000 ; -0.811 ; 14.918 ;; -14.729 ; T80se:z80_inst|T80:u0|F[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[6][1] ; SW[15] ; SW[15] ; 1.000 ; -0.786 ; 14.941 ;; -14.728 ; T80se:z80_inst|T80:u0|IR[3] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[1][6] ; SW[15] ; SW[15] ; 1.000 ; -0.812 ; 14.914 ;; -14.727 ; T80se:z80_inst|T80:u0|F[6] ; T80se:z80_inst|T80:u0|IncDecZ ; SW[15] ; SW[15] ; 1.000 ; -0.796 ; 14.929 ;; -14.727 ; T80se:z80_inst|T80:u0|F[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[4][1] ; SW[15] ; SW[15] ; 1.000 ; -0.786 ; 14.939 ;; -14.724 ; T80se:z80_inst|T80:u0|F[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[1][3] ; SW[15] ; SW[15] ; 1.000 ; -0.789 ; 14.933 ;; -14.722 ; T80se:z80_inst|T80:u0|F[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[2][3] ; SW[15] ; SW[15] ; 1.000 ; -0.789 ; 14.931 ;; -14.700 ; T80se:z80_inst|T80:u0|F[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[7][7] ; SW[15] ; SW[15] ; 1.000 ; -0.785 ; 14.913 ;; -14.669 ; T80se:z80_inst|T80:u0|MCycle[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[5][6] ; SW[15] ; SW[15] ; 1.000 ; -0.814 ; 14.853 ;; -14.669 ; T80se:z80_inst|T80:u0|MCycle[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[6][6] ; SW[15] ; SW[15] ; 1.000 ; -0.814 ; 14.853 ;; -14.658 ; T80se:z80_inst|T80:u0|IR[2] ; T80se:z80_inst|T80:u0|IncDecZ ; SW[15] ; SW[15] ; 1.000 ; -0.818 ; 14.838 ;; -14.655 ; T80se:z80_inst|T80:u0|IR[1] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[1][6] ; SW[15] ; SW[15] ; 1.000 ; -0.811 ; 14.842 ;; -14.649 ; T80se:z80_inst|T80:u0|IR[6] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[1][6] ; SW[15] ; SW[15] ; 1.000 ; -0.811 ; 14.836 ;; -14.647 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[0][6] ; SW[15] ; SW[15] ; 1.000 ; -0.787 ; 14.858 ;; -14.642 ; T80se:z80_inst|T80:u0|F[6] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[7][1] ; SW[15] ; SW[15] ; 1.000 ; -0.789 ; 14.851 ;; -14.641 ; T80se:z80_inst|T80:u0|F[6] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[5][1] ; SW[15] ; SW[15] ; 1.000 ; -0.789 ; 14.850 ;; -14.634 ; T80se:z80_inst|T80:u0|IR[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[5][6] ; SW[15] ; SW[15] ; 1.000 ; -0.814 ; 14.818 ;; -14.634 ; T80se:z80_inst|T80:u0|IR[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[6][6] ; SW[15] ; SW[15] ; 1.000 ; -0.814 ; 14.818 ;; -14.633 ; T80se:z80_inst|T80:u0|F[6] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[6][1] ; SW[15] ; SW[15] ; 1.000 ; -0.787 ; 14.844 ;; -14.631 ; T80se:z80_inst|T80:u0|F[6] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[4][1] ; SW[15] ; SW[15] ; 1.000 ; -0.787 ; 14.842 ;; -14.628 ; T80se:z80_inst|T80:u0|F[6] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[1][3] ; SW[15] ; SW[15] ; 1.000 ; -0.790 ; 14.836 ;; -14.626 ; T80se:z80_inst|T80:u0|F[6] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[2][3] ; SW[15] ; SW[15] ; 1.000 ; -0.790 ; 14.834 ;; -14.613 ; T80se:z80_inst|T80:u0|F[7] ; T80se:z80_inst|T80:u0|IncDecZ ; SW[15] ; SW[15] ; 1.000 ; -0.796 ; 14.815 ;; -14.611 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[5][3] ; SW[15] ; SW[15] ; 1.000 ; -0.785 ; 14.824 ;; -14.608 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[7][3] ; SW[15] ; SW[15] ; 1.000 ; -0.785 ; 14.821 ;; -14.604 ; T80se:z80_inst|T80:u0|F[6] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[7][7] ; SW[15] ; SW[15] ; 1.000 ; -0.786 ; 14.816 ;; -14.596 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[5][7] ; SW[15] ; SW[15] ; 1.000 ; -0.785 ; 14.809 ;; -14.595 ; T80se:z80_inst|T80:u0|MCycle[1] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[5][6] ; SW[15] ; SW[15] ; 1.000 ; -0.814 ; 14.779 ;; -14.595 ; T80se:z80_inst|T80:u0|MCycle[1] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[6][6] ; SW[15] ; SW[15] ; 1.000 ; -0.814 ; 14.779 ;; -14.595 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[7][7] ; SW[15] ; SW[15] ; 1.000 ; -0.785 ; 14.808 ;; -14.585 ; T80se:z80_inst|T80:u0|IR[4] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[5][6] ; SW[15] ; SW[15] ; 1.000 ; -0.815 ; 14.768 ;; -14.585 ; T80se:z80_inst|T80:u0|IR[4] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[6][6] ; SW[15] ; SW[15] ; 1.000 ; -0.815 ; 14.768 ;; -14.576 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[6][4] ; SW[15] ; SW[15] ; 1.000 ; -0.785 ; 14.789 ;; -14.576 ; T80se:z80_inst|T80:u0|F[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[4][4] ; SW[15] ; SW[15] ; 1.000 ; -0.785 ; 14.789 ;; -14.576 ; T80se:z80_inst|T80:u0|IR[7] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[5][6] ; SW[15] ; SW[15] ; 1.000 ; -0.803 ; 14.771 ;; -14.576 ; T80se:z80_inst|T80:u0|IR[7] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[6][6] ; SW[15] ; SW[15] ; 1.000 ; -0.803 ; 14.771 ;; -14.573 ; T80se:z80_inst|T80:u0|IR[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[7][1] ; SW[15] ; SW[15] ; 1.000 ; -0.811 ; 14.760 ;; -14.572 ; T80se:z80_inst|T80:u0|IR[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[5][1] ; SW[15] ; SW[15] ; 1.000 ; -0.811 ; 14.759 ;; -14.572 ; T80se:z80_inst|T80:u0|MCycle[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsL[3][6] ; SW[15] ; SW[15] ; 1.000 ; -0.809 ; 14.761 ;+---------+---------------------------------+------------------------------------------------+--------------+-------------+--------------+------------+------------++------------------------------------------------------------------------------------------------------------------------------------------+; Setup: 'CLOCK_50' ;+--------+------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;+--------+------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+; -9.393 ; next_char_sig[0] ; LCD:lcd_inst|next_command.print_string ; SW[15] ; CLOCK_50 ; 1.000 ; -6.899 ; 3.472 ;; -9.365 ; next_char_sig[3] ; LCD:lcd_inst|next_command.print_string ; SW[15] ; CLOCK_50 ; 1.000 ; -6.901 ; 3.442 ;; -9.325 ; next_char_sig[1] ; LCD:lcd_inst|next_command.print_string ; SW[15] ; CLOCK_50 ; 1.000 ; -6.902 ; 3.401 ;; -9.312 ; next_char_sig[2] ; LCD:lcd_inst|next_command.print_string ; SW[15] ; CLOCK_50 ; 1.000 ; -6.885 ; 3.405 ;; -9.199 ; next_char_sig[6] ; LCD:lcd_inst|next_command.print_string ; SW[15] ; CLOCK_50 ; 1.000 ; -6.884 ; 3.293 ;; -9.134 ; next_char_sig[7] ; LCD:lcd_inst|next_command.print_string ; SW[15] ; CLOCK_50 ; 1.000 ; -6.887 ; 3.225 ;; -9.075 ; next_char_sig[0] ; LCD:lcd_inst|char_count_sig[2] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.889 ; 3.164 ;; -9.073 ; next_char_sig[4] ; LCD:lcd_inst|next_command.print_string ; SW[15] ; CLOCK_50 ; 1.000 ; -6.900 ; 3.151 ;; -9.052 ; next_char_sig[3] ; LCD:lcd_inst|char_count_sig[2] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.891 ; 3.139 ;; -9.035 ; next_char_sig[0] ; LCD:lcd_inst|data_bus_value[2] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.900 ; 3.113 ;; -9.026 ; next_char_sig[5] ; LCD:lcd_inst|next_command.print_string ; SW[15] ; CLOCK_50 ; 1.000 ; -6.880 ; 3.124 ;; -9.012 ; next_char_sig[1] ; LCD:lcd_inst|char_count_sig[2] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.892 ; 3.098 ;; -8.999 ; next_char_sig[2] ; LCD:lcd_inst|char_count_sig[2] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.875 ; 3.102 ;; -8.978 ; next_char_sig[6] ; LCD:lcd_inst|data_bus_value[2] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.885 ; 3.071 ;; -8.969 ; next_char_sig[1] ; LCD:lcd_inst|data_bus_value[2] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.903 ; 3.044 ;; -8.959 ; next_char_sig[6] ; LCD:lcd_inst|next_command.return_home ; SW[15] ; CLOCK_50 ; 1.000 ; -6.884 ; 3.053 ;; -8.950 ; next_char_sig[7] ; LCD:lcd_inst|data_bus_value[2] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.888 ; 3.040 ;; -8.941 ; next_char_sig[0] ; LCD:lcd_inst|char_count_sig[4] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.888 ; 3.031 ;; -8.940 ; next_char_sig[0] ; LCD:lcd_inst|char_count_sig[3] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.888 ; 3.030 ;; -8.940 ; next_char_sig[0] ; LCD:lcd_inst|char_count_sig[1] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.888 ; 3.030 ;; -8.939 ; next_char_sig[0] ; LCD:lcd_inst|char_count_sig[0] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.888 ; 3.029 ;; -8.929 ; next_char_sig[3] ; LCD:lcd_inst|char_count_sig[4] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.890 ; 3.017 ;; -8.928 ; next_char_sig[3] ; LCD:lcd_inst|char_count_sig[3] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.890 ; 3.016 ;; -8.928 ; next_char_sig[3] ; LCD:lcd_inst|char_count_sig[1] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.890 ; 3.016 ;; -8.927 ; next_char_sig[3] ; LCD:lcd_inst|char_count_sig[0] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.890 ; 3.015 ;; -8.910 ; next_char_sig[2] ; LCD:lcd_inst|data_bus_value[2] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.886 ; 3.002 ;; -8.894 ; next_char_sig[6] ; LCD:lcd_inst|data_bus_value[4] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.884 ; 2.988 ;; -8.894 ; next_char_sig[7] ; LCD:lcd_inst|next_command.return_home ; SW[15] ; CLOCK_50 ; 1.000 ; -6.887 ; 2.985 ;; -8.893 ; next_char_sig[6] ; LCD:lcd_inst|data_bus_value[5] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.884 ; 2.987 ;; -8.889 ; next_char_sig[1] ; LCD:lcd_inst|char_count_sig[4] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.891 ; 2.976 ;; -8.888 ; next_char_sig[1] ; LCD:lcd_inst|char_count_sig[3] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.891 ; 2.975 ;; -8.888 ; next_char_sig[1] ; LCD:lcd_inst|char_count_sig[1] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.891 ; 2.975 ;; -8.887 ; next_char_sig[1] ; LCD:lcd_inst|char_count_sig[0] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.891 ; 2.974 ;; -8.881 ; next_char_sig[6] ; LCD:lcd_inst|char_count_sig[2] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.874 ; 2.985 ;; -8.876 ; next_char_sig[2] ; LCD:lcd_inst|char_count_sig[4] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.874 ; 2.980 ;; -8.875 ; next_char_sig[2] ; LCD:lcd_inst|char_count_sig[3] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.874 ; 2.979 ;; -8.875 ; next_char_sig[2] ; LCD:lcd_inst|char_count_sig[1] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.874 ; 2.979 ;; -8.874 ; next_char_sig[2] ; LCD:lcd_inst|char_count_sig[0] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.874 ; 2.978 ;; -8.869 ; next_char_sig[6] ; LCD:lcd_inst|data_bus_value[3] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.884 ; 2.963 ;; -8.866 ; next_char_sig[7] ; LCD:lcd_inst|data_bus_value[4] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.887 ; 2.957 ;; -8.865 ; next_char_sig[7] ; LCD:lcd_inst|data_bus_value[5] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.887 ; 2.956 ;; -8.855 ; next_char_sig[3] ; LCD:lcd_inst|data_bus_value[2] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.902 ; 2.931 ;; -8.841 ; next_char_sig[7] ; LCD:lcd_inst|data_bus_value[3] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.887 ; 2.932 ;; -8.836 ; next_char_sig[4] ; LCD:lcd_inst|next_command.return_home ; SW[15] ; CLOCK_50 ; 1.000 ; -6.900 ; 2.914 ;; -8.818 ; next_char_sig[6] ; LCD:lcd_inst|data_bus_value[6] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.884 ; 2.912 ;; -8.816 ; next_char_sig[7] ; LCD:lcd_inst|char_count_sig[2] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.877 ; 2.917 ;; -8.790 ; next_char_sig[7] ; LCD:lcd_inst|data_bus_value[6] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.887 ; 2.881 ;; -8.789 ; next_char_sig[5] ; LCD:lcd_inst|next_command.return_home ; SW[15] ; CLOCK_50 ; 1.000 ; -6.880 ; 2.887 ;; -8.760 ; next_char_sig[4] ; LCD:lcd_inst|char_count_sig[2] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.890 ; 2.848 ;; -8.738 ; next_char_sig[6] ; LCD:lcd_inst|char_count_sig[4] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.873 ; 2.843 ;; -8.737 ; next_char_sig[6] ; LCD:lcd_inst|char_count_sig[3] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.873 ; 2.842 ;; -8.737 ; next_char_sig[6] ; LCD:lcd_inst|char_count_sig[1] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.873 ; 2.842 ;; -8.736 ; next_char_sig[6] ; LCD:lcd_inst|char_count_sig[0] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.873 ; 2.841 ;; -8.735 ; next_char_sig[0] ; LCD:lcd_inst|next_command.return_home ; SW[15] ; CLOCK_50 ; 1.000 ; -6.899 ; 2.814 ;; -8.713 ; next_char_sig[5] ; LCD:lcd_inst|char_count_sig[2] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.870 ; 2.821 ;; -8.704 ; next_char_sig[3] ; LCD:lcd_inst|next_command.return_home ; SW[15] ; CLOCK_50 ; 1.000 ; -6.901 ; 2.781 ;; -8.669 ; next_char_sig[7] ; LCD:lcd_inst|char_count_sig[4] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.876 ; 2.771 ;; -8.669 ; next_char_sig[7] ; LCD:lcd_inst|char_count_sig[1] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.876 ; 2.771 ;; -8.668 ; next_char_sig[7] ; LCD:lcd_inst|char_count_sig[3] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.876 ; 2.770 ;; -8.668 ; next_char_sig[7] ; LCD:lcd_inst|char_count_sig[0] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.876 ; 2.770 ;; -8.664 ; next_char_sig[1] ; LCD:lcd_inst|next_command.return_home ; SW[15] ; CLOCK_50 ; 1.000 ; -6.902 ; 2.740 ;; -8.653 ; next_char_sig[2] ; LCD:lcd_inst|next_command.return_home ; SW[15] ; CLOCK_50 ; 1.000 ; -6.885 ; 2.746 ;; -8.637 ; next_char_sig[4] ; LCD:lcd_inst|char_count_sig[4] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.889 ; 2.726 ;; -8.636 ; next_char_sig[4] ; LCD:lcd_inst|char_count_sig[3] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.889 ; 2.725 ;; -8.636 ; next_char_sig[4] ; LCD:lcd_inst|char_count_sig[1] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.889 ; 2.725 ;; -8.635 ; next_char_sig[4] ; LCD:lcd_inst|char_count_sig[0] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.889 ; 2.724 ;; -8.597 ; next_char_sig[6] ; LCD:lcd_inst|data_bus_value[1] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.884 ; 2.691 ;; -8.590 ; next_char_sig[5] ; LCD:lcd_inst|char_count_sig[4] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.869 ; 2.699 ;; -8.589 ; next_char_sig[6] ; LCD:lcd_inst|data_bus_value[0] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.884 ; 2.683 ;; -8.589 ; next_char_sig[5] ; LCD:lcd_inst|char_count_sig[3] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.869 ; 2.698 ;; -8.589 ; next_char_sig[5] ; LCD:lcd_inst|char_count_sig[1] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.869 ; 2.698 ;; -8.588 ; next_char_sig[5] ; LCD:lcd_inst|char_count_sig[0] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.869 ; 2.697 ;; -8.586 ; next_char_sig[5] ; LCD:lcd_inst|data_bus_value[2] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.881 ; 2.683 ;; -8.581 ; next_char_sig[1] ; LCD:lcd_inst|data_bus_value[0] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.902 ; 2.657 ;; -8.569 ; next_char_sig[7] ; LCD:lcd_inst|data_bus_value[1] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.887 ; 2.660 ;; -8.561 ; next_char_sig[7] ; LCD:lcd_inst|data_bus_value[0] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.887 ; 2.652 ;; -8.559 ; next_char_sig[1] ; LCD:lcd_inst|data_bus_value[1] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.902 ; 2.635 ;; -8.522 ; next_char_sig[2] ; LCD:lcd_inst|data_bus_value[0] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.885 ; 2.615 ;; -8.508 ; next_char_sig[4] ; LCD:lcd_inst|data_bus_value[2] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.901 ; 2.585 ;; -8.501 ; next_char_sig[5] ; LCD:lcd_inst|data_bus_value[4] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.880 ; 2.599 ;; -8.501 ; next_char_sig[5] ; LCD:lcd_inst|data_bus_value[5] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.880 ; 2.599 ;; -8.500 ; next_char_sig[2] ; LCD:lcd_inst|data_bus_value[1] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.885 ; 2.593 ;; -8.480 ; next_char_sig[5] ; LCD:lcd_inst|data_bus_value[3] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.880 ; 2.578 ;; -8.467 ; next_char_sig[3] ; LCD:lcd_inst|data_bus_value[0] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.901 ; 2.544 ;; -8.445 ; next_char_sig[3] ; LCD:lcd_inst|data_bus_value[1] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.901 ; 2.522 ;; -8.438 ; next_char_sig[5] ; LCD:lcd_inst|data_bus_value[6] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.880 ; 2.536 ;; -8.425 ; next_char_sig[2] ; LCD:lcd_inst|data_bus_value[4] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.885 ; 2.518 ;; -8.425 ; next_char_sig[2] ; LCD:lcd_inst|data_bus_value[5] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.885 ; 2.518 ;; -8.423 ; next_char_sig[4] ; LCD:lcd_inst|data_bus_value[4] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.900 ; 2.501 ;; -8.423 ; next_char_sig[4] ; LCD:lcd_inst|data_bus_value[5] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.900 ; 2.501 ;; -8.402 ; next_char_sig[4] ; LCD:lcd_inst|data_bus_value[3] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.900 ; 2.480 ;; -8.360 ; next_char_sig[4] ; LCD:lcd_inst|data_bus_value[6] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.900 ; 2.438 ;; -8.310 ; next_char_sig[1] ; LCD:lcd_inst|data_bus_value[3] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.902 ; 2.386 ;; -8.296 ; next_char_sig[1] ; LCD:lcd_inst|data_bus_value[6] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.902 ; 2.372 ;; -8.251 ; next_char_sig[2] ; LCD:lcd_inst|data_bus_value[3] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.885 ; 2.344 ;; -8.237 ; next_char_sig[2] ; LCD:lcd_inst|data_bus_value[6] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.885 ; 2.330 ;; -8.204 ; next_char_sig[5] ; LCD:lcd_inst|data_bus_value[1] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.880 ; 2.302 ;; -8.200 ; next_char_sig[3] ; LCD:lcd_inst|data_bus_value[4] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.901 ; 2.277 ;; -8.200 ; next_char_sig[3] ; LCD:lcd_inst|data_bus_value[5] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.901 ; 2.277 ;; -8.198 ; next_char_sig[5] ; LCD:lcd_inst|data_bus_value[0] ; SW[15] ; CLOCK_50 ; 1.000 ; -6.880 ; 2.296 ;+--------+------------------+----------------------------------------+--------------+-------------+--------------+------------+------------++---------------------------------------------------------------------------------------------------------------------------------------+; Setup: 'T80se:z80_inst|MREQ_n' ;+--------+-----------------------------+----------------+--------------+-----------------------+--------------+------------+------------+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;+--------+-----------------------------+----------------+--------------+-----------------------+--------------+------------+------------+; -6.449 ; T80se:z80_inst|T80:u0|DO[1] ; lcdvram[1][1] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.922 ; 1.777 ;; -5.903 ; T80se:z80_inst|T80:u0|DO[0] ; lcdvram[22][0] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -3.362 ; 2.319 ;; -5.737 ; T80se:z80_inst|T80:u0|DO[1] ; lcdvram[17][1] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.873 ; 2.099 ;; -5.700 ; T80se:z80_inst|T80:u0|DO[4] ; lcdvram[22][4] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -3.300 ; 1.725 ;; -5.679 ; T80se:z80_inst|T80:u0|DO[4] ; lcdvram[15][4] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.862 ; 2.148 ;; -5.669 ; T80se:z80_inst|T80:u0|DO[5] ; lcdvram[11][5] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -3.022 ; 2.425 ;; -5.652 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[22][3] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -3.549 ; 1.569 ;; -5.635 ; T80se:z80_inst|T80:u0|DO[4] ; lcdvram[12][4] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -3.155 ; 2.150 ;; -5.628 ; T80se:z80_inst|T80:u0|DO[5] ; lcdvram[25][5] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.939 ; 2.153 ;; -5.626 ; T80se:z80_inst|T80:u0|DO[5] ; lcdvram[17][5] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.621 ; 2.790 ;; -5.623 ; T80se:z80_inst|T80:u0|DO[1] ; lcdvram[15][1] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -3.046 ; 2.076 ;; -5.617 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[1][3] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -3.064 ; 2.145 ;; -5.605 ; T80se:z80_inst|T80:u0|DO[0] ; lcdvram[11][0] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.964 ; 2.239 ;; -5.593 ; T80se:z80_inst|T80:u0|DO[4] ; lcdvram[29][4] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.864 ; 2.052 ;; -5.579 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[12][7] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -3.057 ; 2.193 ;; -5.575 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[12][3] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.967 ; 2.077 ;; -5.572 ; T80se:z80_inst|T80:u0|DO[6] ; lcdvram[15][6] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.866 ; 2.037 ;; -5.570 ; T80se:z80_inst|T80:u0|DO[0] ; lcdvram[12][0] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -3.057 ; 2.184 ;; -5.562 ; T80se:z80_inst|T80:u0|DO[1] ; lcdvram[12][1] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.954 ; 2.073 ;; -5.547 ; T80se:z80_inst|T80:u0|DO[6] ; lcdvram[12][6] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.971 ; 2.038 ;; -5.536 ; T80se:z80_inst|T80:u0|DO[5] ; lcdvram[14][5] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.894 ; 1.967 ;; -5.522 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[29][2] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -3.005 ; 2.295 ;; -5.518 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[11][3] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.897 ; 2.115 ;; -5.478 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[15][2] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -3.057 ; 2.070 ;; -5.476 ; T80se:z80_inst|T80:u0|DO[6] ; lcdvram[22][6] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -3.222 ; 1.894 ;; -5.466 ; T80se:z80_inst|T80:u0|DO[0] ; lcdvram[14][0] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.796 ; 2.001 ;; -5.454 ; T80se:z80_inst|T80:u0|DO[0] ; lcdvram[15][0] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.793 ; 2.324 ;; -5.438 ; T80se:z80_inst|T80:u0|DO[0] ; lcdvram[25][0] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.943 ; 2.275 ;; -5.433 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[11][7] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.835 ; 2.262 ;; -5.429 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[25][7] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.965 ; 2.102 ;; -5.412 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[25][3] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.836 ; 2.241 ;; -5.410 ; T80se:z80_inst|T80:u0|DO[6] ; lcdvram[14][6] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.883 ; 2.308 ;; -5.405 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[14][3] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -3.204 ; 1.974 ;; -5.398 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[1][7] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.846 ; 2.150 ;; -5.386 ; T80se:z80_inst|T80:u0|DO[1] ; lcdvram[13][1] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -3.033 ; 1.947 ;; -5.386 ; T80se:z80_inst|T80:u0|DO[4] ; lcdvram[11][4] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.829 ; 2.220 ;; -5.381 ; T80se:z80_inst|T80:u0|DO[1] ; lcdvram[14][1] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -3.606 ; 1.554 ;; -5.370 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[15][7] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.808 ; 2.336 ;; -5.360 ; T80se:z80_inst|T80:u0|DO[4] ; lcdvram[14][4] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.882 ; 2.259 ;; -5.346 ; T80se:z80_inst|T80:u0|DO[1] ; lcdvram[22][1] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -3.408 ; 1.578 ;; -5.346 ; T80se:z80_inst|T80:u0|DO[6] ; lcdvram[25][6] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -3.104 ; 1.909 ;; -5.340 ; T80se:z80_inst|T80:u0|DO[6] ; lcdvram[29][6] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -3.005 ; 1.975 ;; -5.338 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[22][7] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -3.230 ; 1.749 ;; -5.337 ; T80se:z80_inst|T80:u0|DO[5] ; lcdvram[29][5] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -3.005 ; 1.800 ;; -5.334 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[14][7] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.732 ; 2.380 ;; -5.332 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[17][3] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.761 ; 2.243 ;; -5.329 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[12][2] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.853 ; 2.139 ;; -5.323 ; T80se:z80_inst|T80:u0|DO[1] ; lcdvram[11][1] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -3.048 ; 1.918 ;; -5.321 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[15][3] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.386 ; 2.713 ;; -5.319 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[22][2] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -3.227 ; 1.735 ;; -5.309 ; T80se:z80_inst|T80:u0|DO[4] ; lcdvram[25][4] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.935 ; 1.834 ;; -5.308 ; T80se:z80_inst|T80:u0|DO[0] ; lcdvram[31][0] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -1.309 ; 3.591 ;; -5.306 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[14][2] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -3.423 ; 1.550 ;; -5.302 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[13][7] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.980 ; 1.914 ;; -5.299 ; T80se:z80_inst|T80:u0|DO[5] ; lcdvram[21][5] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.435 ; 2.637 ;; -5.290 ; T80se:z80_inst|T80:u0|DO[5] ; lcdvram[3][5] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -3.343 ; 1.719 ;; -5.281 ; T80se:z80_inst|T80:u0|DO[1] ; lcdvram[21][1] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.406 ; 2.068 ;; -5.271 ; T80se:z80_inst|T80:u0|DO[0] ; lcdvram[13][0] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.979 ; 1.892 ;; -5.271 ; T80se:z80_inst|T80:u0|DO[1] ; lcdvram[25][1] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.946 ; 2.103 ;; -5.268 ; T80se:z80_inst|T80:u0|DO[5] ; lcdvram[22][5] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -3.549 ; 1.498 ;; -5.257 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[29][3] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.888 ; 2.032 ;; -5.257 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[21][7] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.414 ; 2.439 ;; -5.254 ; T80se:z80_inst|T80:u0|DO[6] ; lcdvram[1][6] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.923 ; 1.793 ;; -5.232 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[3][2] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -3.073 ; 1.823 ;; -5.230 ; T80se:z80_inst|T80:u0|DO[5] ; lcdvram[23][5] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -1.957 ; 2.874 ;; -5.229 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[17][7] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.948 ; 1.956 ;; -5.222 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[25][2] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.964 ; 2.038 ;; -5.216 ; T80se:z80_inst|T80:u0|DO[5] ; lcdvram[12][5] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.969 ; 2.025 ;; -5.214 ; T80se:z80_inst|T80:u0|DO[6] ; lcdvram[11][6] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.931 ; 2.062 ;; -5.213 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[1][2] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -3.063 ; 1.742 ;; -5.210 ; T80se:z80_inst|T80:u0|DO[4] ; lcdvram[13][4] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.725 ; 2.127 ;; -5.203 ; T80se:z80_inst|T80:u0|DO[0] ; lcdvram[7][0] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -1.355 ; 3.447 ;; -5.201 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[7][7] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -1.339 ; 3.454 ;; -5.197 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[23][3] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -1.918 ; 2.875 ;; -5.197 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[11][2] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -3.394 ; 1.469 ;; -5.194 ; T80se:z80_inst|T80:u0|DO[6] ; lcdvram[17][6] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.951 ; 1.908 ;; -5.192 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[13][2] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.691 ; 2.166 ;; -5.186 ; T80se:z80_inst|T80:u0|DO[1] ; lcdvram[29][1] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.867 ; 2.099 ;; -5.186 ; T80se:z80_inst|T80:u0|DO[1] ; lcdvram[9][1] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -1.706 ; 3.072 ;; -5.162 ; T80se:z80_inst|T80:u0|DO[6] ; lcdvram[7][6] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -1.380 ; 3.374 ;; -5.160 ; T80se:z80_inst|T80:u0|DO[4] ; lcdvram[17][4] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.913 ; 2.025 ;; -5.154 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[17][2] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.895 ; 2.038 ;; -5.151 ; T80se:z80_inst|T80:u0|DO[6] ; lcdvram[13][6] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.586 ; 2.343 ;; -5.136 ; T80se:z80_inst|T80:u0|DO[1] ; lcdvram[3][1] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.934 ; 1.867 ;; -5.135 ; T80se:z80_inst|T80:u0|DO[5] ; lcdvram[13][5] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.709 ; 1.937 ;; -5.124 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[9][3] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -1.703 ; 3.022 ;; -5.114 ; T80se:z80_inst|T80:u0|DO[5] ; lcdvram[15][5] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.994 ; 1.905 ;; -5.112 ; T80se:z80_inst|T80:u0|DO[6] ; lcdvram[31][6] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -1.287 ; 3.419 ;; -5.106 ; T80se:z80_inst|T80:u0|DO[4] ; lcdvram[1][4] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.839 ; 1.761 ;; -5.097 ; T80se:z80_inst|T80:u0|DO[0] ; lcdvram[17][0] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.915 ; 1.961 ;; -5.081 ; T80se:z80_inst|T80:u0|DO[4] ; lcdvram[7][4] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -1.350 ; 3.329 ;; -5.078 ; T80se:z80_inst|T80:u0|DO[0] ; lcdvram[29][0] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.885 ; 1.858 ;; -5.075 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[9][2] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -1.701 ; 2.979 ;; -5.074 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[29][7] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.889 ; 1.848 ;; -5.071 ; T80se:z80_inst|T80:u0|DO[0] ; lcdvram[3][0] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.899 ; 1.815 ;; -5.061 ; T80se:z80_inst|T80:u0|DO[6] ; lcdvram[3][6] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.931 ; 1.795 ;; -5.055 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[21][3] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.411 ; 2.243 ;; -5.053 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[3][3] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -3.061 ; 1.770 ;; -5.052 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[7][3] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -1.339 ; 3.312 ;; -5.050 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[13][3] ; SW[15] ; T80se:z80_inst|MREQ_n ; 0.500 ; -2.662 ; 2.029 ;+--------+-----------------------------+----------------+--------------+-----------------------+--------------+------------+------------++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Setup: 'clk_div:clkdiv_inst|clock_25MHz' ;+--------+-------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+---------------------------------+---------------------------------+--------------+------------+------------+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;+--------+-------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+---------------------------------+---------------------------------+--------------+------------+------------+; -5.761 ; charram:cram|altsyncram:altsyncram_component|altsyncram_l4o1:auto_generated|ram_block1a0~portb_address_reg0 ; video:video_inst|VGA_SYNC:vga_sync_inst|blue_out[1] ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -0.371 ; 6.388 ;; -5.761 ; charram:cram|altsyncram:altsyncram_component|altsyncram_l4o1:auto_generated|ram_block1a0~portb_address_reg0 ; video:video_inst|VGA_SYNC:vga_sync_inst|blue_out[2] ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -0.371 ; 6.388 ;; -5.761 ; charram:cram|altsyncram:altsyncram_component|altsyncram_l4o1:auto_generated|ram_block1a0~portb_address_reg0 ; video:video_inst|VGA_SYNC:vga_sync_inst|blue_out[3] ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -0.371 ; 6.388 ;; -5.513 ; charram:cram|altsyncram:altsyncram_component|altsyncram_l4o1:auto_generated|ram_block1a4~portb_address_reg0 ; video:video_inst|VGA_SYNC:vga_sync_inst|blue_out[1] ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -0.374 ; 6.137 ;; -5.512 ; charram:cram|altsyncram:altsyncram_component|altsyncram_l4o1:auto_generated|ram_block1a4~portb_address_reg0 ; video:video_inst|VGA_SYNC:vga_sync_inst|blue_out[2] ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -0.374 ; 6.136 ;; -5.512 ; charram:cram|altsyncram:altsyncram_component|altsyncram_l4o1:auto_generated|ram_block1a4~portb_address_reg0 ; video:video_inst|VGA_SYNC:vga_sync_inst|blue_out[3] ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -0.374 ; 6.136 ;; -5.386 ; charram:cram|altsyncram:altsyncram_component|altsyncram_l4o1:auto_generated|ram_block1a0~portb_address_reg0 ; video:video_inst|VGA_SYNC:vga_sync_inst|blue_out[0] ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -0.371 ; 6.013 ;; -5.137 ; charram:cram|altsyncram:altsyncram_component|altsyncram_l4o1:auto_generated|ram_block1a4~portb_address_reg0 ; video:video_inst|VGA_SYNC:vga_sync_inst|blue_out[0] ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -0.374 ; 5.761 ;; -4.975 ; T80se:z80_inst|T80:u0|A[12] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a0~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -3.212 ; 2.791 ;; -4.961 ; T80se:z80_inst|T80:u0|A[12] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a3~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -3.207 ; 2.782 ;; -4.934 ; T80se:z80_inst|T80:u0|A[12] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a10~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -3.208 ; 2.754 ;; -4.927 ; T80se:z80_inst|T80:u0|A[12] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a9~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -3.209 ; 2.746 ;; -4.895 ; T80se:z80_inst|T80:u0|A[11] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a11~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -3.224 ; 2.699 ;; -4.884 ; T80se:z80_inst|T80:u0|A[12] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a11~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -3.224 ; 2.688 ;; -4.869 ; T80se:z80_inst|T80:u0|A[12] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a7~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -3.206 ; 2.691 ;; -4.706 ; T80se:z80_inst|T80:u0|A[11] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a7~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -3.206 ; 2.528 ;; -4.691 ; T80se:z80_inst|T80:u0|A[11] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a9~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -3.209 ; 2.510 ;; -4.680 ; T80se:z80_inst|T80:u0|A[11] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a10~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -3.208 ; 2.500 ;; -4.665 ; T80se:z80_inst|T80:u0|A[12] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a14~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -3.233 ; 2.460 ;; -4.658 ; T80se:z80_inst|T80:u0|A[11] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a2~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -3.221 ; 2.465 ;; -4.656 ; T80se:z80_inst|T80:u0|A[11] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a3~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -3.207 ; 2.477 ;; -4.652 ; T80se:z80_inst|T80:u0|A[12] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a12~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -3.228 ; 2.452 ;; -4.629 ; T80se:z80_inst|T80:u0|A[12] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a15~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -3.225 ; 2.432 ;; -4.618 ; T80se:z80_inst|T80:u0|A[11] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a1~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -3.214 ; 2.432 ;; -4.616 ; T80se:z80_inst|T80:u0|A[11] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a12~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -3.228 ; 2.416 ;; -4.611 ; T80se:z80_inst|T80:u0|A[11] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a15~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -3.225 ; 2.414 ;; -4.605 ; T80se:z80_inst|T80:u0|A[12] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a13~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -3.226 ; 2.407 ;; -4.599 ; T80se:z80_inst|T80:u0|A[11] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a4~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -3.210 ; 2.417 ;; -4.596 ; T80se:z80_inst|T80:u0|A[11] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a14~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -3.233 ; 2.391 ;; -4.591 ; T80se:z80_inst|T80:u0|A[12] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a6~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -3.223 ; 2.396 ;; -4.590 ; T80se:z80_inst|T80:u0|A[12] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a2~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -3.221 ; 2.397 ;; -4.585 ; T80se:z80_inst|T80:u0|A[12] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a8~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -3.224 ; 2.389 ;; -4.576 ; T80se:z80_inst|T80:u0|A[12] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a1~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -3.214 ; 2.390 ;; -4.567 ; T80se:z80_inst|T80:u0|A[11] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a13~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -3.226 ; 2.369 ;; -4.557 ; T80se:z80_inst|T80:u0|A[11] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a6~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -3.223 ; 2.362 ;; -4.557 ; T80se:z80_inst|T80:u0|A[12] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a5~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -3.209 ; 2.376 ;; -4.557 ; T80se:z80_inst|T80:u0|A[12] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a4~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -3.210 ; 2.375 ;; -4.550 ; T80se:z80_inst|T80:u0|A[11] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a0~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -3.212 ; 2.366 ;; -4.542 ; T80se:z80_inst|T80:u0|A[11] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a5~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -3.209 ; 2.361 ;; -4.522 ; T80se:z80_inst|T80:u0|A[11] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a8~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -3.224 ; 2.326 ;; -4.511 ; T80se:z80_inst|T80:u0|A[10] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a7~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.654 ; 2.885 ;; -4.508 ; T80se:z80_inst|T80:u0|A[9] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a0~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.660 ; 2.876 ;; -4.467 ; T80se:z80_inst|T80:u0|A[9] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a7~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.654 ; 2.841 ;; -4.458 ; T80se:z80_inst|T80:u0|A[5] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a3~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.959 ; 2.527 ;; -4.442 ; T80se:z80_inst|T80:u0|A[5] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a0~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.964 ; 2.506 ;; -4.437 ; T80se:z80_inst|T80:u0|A[9] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a11~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.672 ; 2.793 ;; -4.430 ; T80se:z80_inst|T80:u0|A[10] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a11~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.672 ; 2.786 ;; -4.425 ; T80se:z80_inst|T80:u0|A[9] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a4~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.658 ; 2.795 ;; -4.424 ; T80se:z80_inst|T80:u0|A[5] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a1~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.966 ; 2.486 ;; -4.416 ; T80se:z80_inst|T80:u0|A[5] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a14~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.985 ; 2.459 ;; -4.403 ; T80se:z80_inst|T80:u0|A[5] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a12~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.980 ; 2.451 ;; -4.396 ; T80se:z80_inst|T80:u0|A[5] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a2~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.973 ; 2.451 ;; -4.388 ; T80se:z80_inst|T80:u0|A[5] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a13~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.978 ; 2.438 ;; -4.387 ; T80se:z80_inst|T80:u0|A[5] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a10~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.960 ; 2.455 ;; -4.387 ; T80se:z80_inst|T80:u0|A[5] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a4~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.962 ; 2.453 ;; -4.358 ; T80se:z80_inst|T80:u0|A[6] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a12~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.980 ; 2.406 ;; -4.351 ; T80se:z80_inst|T80:u0|A[5] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a11~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.976 ; 2.403 ;; -4.345 ; T80se:z80_inst|T80:u0|A[5] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a6~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.975 ; 2.398 ;; -4.340 ; T80se:z80_inst|T80:u0|A[5] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a8~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.976 ; 2.392 ;; -4.340 ; T80se:z80_inst|T80:u0|A[5] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a15~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.977 ; 2.391 ;; -4.338 ; T80se:z80_inst|T80:u0|A[6] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a15~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.977 ; 2.389 ;; -4.335 ; T80se:z80_inst|T80:u0|A[6] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a14~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.985 ; 2.378 ;; -4.334 ; T80se:z80_inst|T80:u0|A[6] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a13~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.978 ; 2.384 ;; -4.326 ; T80se:z80_inst|T80:u0|A[6] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a9~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.961 ; 2.393 ;; -4.323 ; T80se:z80_inst|T80:u0|A[6] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a6~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.975 ; 2.376 ;; -4.322 ; T80se:z80_inst|T80:u0|A[6] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a2~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.973 ; 2.377 ;; -4.317 ; T80se:z80_inst|T80:u0|A[6] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a8~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.976 ; 2.369 ;; -4.312 ; T80se:z80_inst|T80:u0|A[6] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a10~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.960 ; 2.380 ;; -4.310 ; T80se:z80_inst|T80:u0|A[6] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a11~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.976 ; 2.362 ;; -4.301 ; T80se:z80_inst|T80:u0|A[6] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a3~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.959 ; 2.370 ;; -4.296 ; T80se:z80_inst|T80:u0|A[13] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a0~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.354 ; 2.970 ;; -4.295 ; T80se:z80_inst|T80:u0|A[4] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a2~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.701 ; 2.622 ;; -4.275 ; T80se:z80_inst|T80:u0|A[6] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a5~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.961 ; 2.342 ;; -4.260 ; T80se:z80_inst|T80:u0|A[2] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a7~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.686 ; 2.602 ;; -4.253 ; T80se:z80_inst|T80:u0|A[10] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a2~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.669 ; 2.612 ;; -4.247 ; T80se:z80_inst|T80:u0|A[5] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a9~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.961 ; 2.314 ;; -4.245 ; T80se:z80_inst|T80:u0|A[13] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a4~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.352 ; 2.921 ;; -4.238 ; T80se:z80_inst|T80:u0|A[6] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a1~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.966 ; 2.300 ;; -4.236 ; T80se:z80_inst|T80:u0|A[4] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a8~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.704 ; 2.560 ;; -4.231 ; T80se:z80_inst|T80:u0|A[10] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a12~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.676 ; 2.583 ;; -4.230 ; T80se:z80_inst|T80:u0|A[6] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a0~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.964 ; 2.294 ;; -4.225 ; T80se:z80_inst|T80:u0|A[9] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a8~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.672 ; 2.581 ;; -4.224 ; T80se:z80_inst|T80:u0|A[10] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a13~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.674 ; 2.578 ;; -4.220 ; T80se:z80_inst|T80:u0|A[9] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a13~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.674 ; 2.574 ;; -4.219 ; T80se:z80_inst|T80:u0|A[2] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a14~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.713 ; 2.534 ;; -4.218 ; T80se:z80_inst|T80:u0|A[5] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a7~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.958 ; 2.288 ;; -4.214 ; T80se:z80_inst|T80:u0|A[9] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a14~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.681 ; 2.561 ;; -4.210 ; T80se:z80_inst|T80:u0|A[9] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a3~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.655 ; 2.583 ;; -4.209 ; T80se:z80_inst|T80:u0|A[10] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a14~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.681 ; 2.556 ;; -4.205 ; T80se:z80_inst|T80:u0|A[3] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a15~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.705 ; 2.528 ;; -4.203 ; T80se:z80_inst|T80:u0|A[9] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a12~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.676 ; 2.555 ;; -4.200 ; T80se:z80_inst|T80:u0|A[3] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a13~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.706 ; 2.522 ;; -4.199 ; T80se:z80_inst|T80:u0|A[0] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a8~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.397 ; 2.830 ;; -4.194 ; T80se:z80_inst|T80:u0|A[1] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a14~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.713 ; 2.509 ;; -4.193 ; T80se:z80_inst|T80:u0|A[4] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a11~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.704 ; 2.517 ;; -4.188 ; T80se:z80_inst|T80:u0|A[2] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a3~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.687 ; 2.529 ;; -4.188 ; T80se:z80_inst|T80:u0|A[10] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a10~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.656 ; 2.560 ;; -4.187 ; T80se:z80_inst|T80:u0|A[10] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a6~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.671 ; 2.544 ;; -4.183 ; T80se:z80_inst|T80:u0|A[10] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a8~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.672 ; 2.539 ;; -4.183 ; T80se:z80_inst|T80:u0|A[6] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a4~porta_address_reg0 ; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 1.000 ; -2.962 ; 2.249 ;+--------+-------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+---------------------------------+---------------------------------+--------------+------------+------------++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Setup: 'ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered' ;+--------+-------------------------------------------------+----------------------------------------------------+-------------------------------------------------------------+-------------------------------------------------------------+--------------+------------+------------+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;+--------+-------------------------------------------------+----------------------------------------------------+-------------------------------------------------------------+-------------------------------------------------------------+--------------+------------+------------+; -2.090 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[5] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.076 ; 3.012 ;; -2.085 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[7] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.078 ; 3.005 ;; -2.085 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[6] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.078 ; 3.005 ;; -2.079 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[5] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.076 ; 3.001 ;; -2.074 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[7] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.078 ; 2.994 ;; -2.074 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[6] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.078 ; 2.994 ;; -1.927 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.080 ; 2.845 ;; -1.918 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.080 ; 2.836 ;; -1.895 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[5] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.076 ; 2.817 ;; -1.890 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[7] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.078 ; 2.810 ;; -1.890 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[6] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.078 ; 2.810 ;; -1.794 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.076 ; 2.716 ;; -1.794 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.076 ; 2.716 ;; -1.794 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[4] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.076 ; 2.716 ;; -1.794 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.076 ; 2.716 ;; -1.794 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.076 ; 2.716 ;; -1.783 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.076 ; 2.705 ;; -1.783 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.076 ; 2.705 ;; -1.783 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[4] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.076 ; 2.705 ;; -1.783 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.076 ; 2.705 ;; -1.783 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.076 ; 2.705 ;; -1.780 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[5] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.076 ; 2.702 ;; -1.775 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[7] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.078 ; 2.695 ;; -1.775 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[6] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.078 ; 2.695 ;; -1.731 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.080 ; 2.649 ;; -1.707 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[5] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.076 ; 2.629 ;; -1.691 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[7] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.078 ; 2.611 ;; -1.691 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[6] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.078 ; 2.611 ;; -1.622 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.080 ; 2.540 ;; -1.613 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[8] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.532 ;; -1.613 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[7] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.532 ;; -1.613 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[6] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.532 ;; -1.613 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[5] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.532 ;; -1.613 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[4] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.532 ;; -1.613 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.532 ;; -1.613 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.532 ;; -1.613 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.532 ;; -1.613 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.532 ;; -1.604 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[8] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.523 ;; -1.604 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[7] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.523 ;; -1.604 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[6] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.523 ;; -1.604 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[5] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.523 ;; -1.604 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[4] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.523 ;; -1.604 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.523 ;; -1.604 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.523 ;; -1.604 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.523 ;; -1.604 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.523 ;; -1.599 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.076 ; 2.521 ;; -1.599 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.076 ; 2.521 ;; -1.599 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[4] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.076 ; 2.521 ;; -1.599 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.076 ; 2.521 ;; -1.599 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.076 ; 2.521 ;; -1.588 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.080 ; 2.506 ;; -1.484 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.076 ; 2.406 ;; -1.484 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.076 ; 2.406 ;; -1.484 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[4] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.076 ; 2.406 ;; -1.484 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.076 ; 2.406 ;; -1.484 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.076 ; 2.406 ;; -1.417 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.076 ; 2.339 ;; -1.417 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.076 ; 2.339 ;; -1.417 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[4] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.076 ; 2.339 ;; -1.417 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.076 ; 2.339 ;; -1.417 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.076 ; 2.339 ;; -1.417 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[8] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.336 ;; -1.417 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[7] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.336 ;; -1.417 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[6] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.336 ;; -1.417 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[5] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.336 ;; -1.417 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[4] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.336 ;; -1.417 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.336 ;; -1.417 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.336 ;; -1.417 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.336 ;; -1.417 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.336 ;; -1.308 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[8] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.227 ;; -1.308 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[7] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.227 ;; -1.308 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[6] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.227 ;; -1.308 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[5] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.227 ;; -1.308 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[4] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.227 ;; -1.308 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.227 ;; -1.308 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.227 ;; -1.308 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.227 ;; -1.308 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.227 ;; -1.205 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[8] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.124 ;; -1.205 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[7] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.124 ;; -1.205 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[6] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.124 ;; -1.205 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[5] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.124 ;; -1.205 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[4] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.124 ;; -1.205 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.124 ;; -1.205 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.124 ;; -1.205 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.124 ;; -1.205 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.079 ; 2.124 ;; -1.096 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.080 ; 2.014 ;; -1.087 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.080 ; 2.005 ;; -1.081 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.080 ; 1.999 ;; -1.080 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.080 ; 1.998 ;; -1.079 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.080 ; 1.997 ;; -1.072 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.080 ; 1.990 ;; -1.071 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.080 ; 1.989 ;; -1.070 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.080 ; 1.988 ;; -0.923 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.080 ; 1.841 ;; -0.914 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000 ; -0.080 ; 1.832 ;+--------+-------------------------------------------------+----------------------------------------------------+-------------------------------------------------------------+-------------------------------------------------------------+--------------+------------+------------++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Setup: 'clk_div:clkdiv_inst|clock_25Mhz_int' ;+--------+-----------------------------------+------------------------------------+-------------------------------------+-------------------------------------+--------------+------------+------------+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;+--------+-----------------------------------+------------------------------------+-------------------------------------+-------------------------------------+--------------+------------+------------+; -0.895 ; clk_div:clkdiv_inst|count_1Mhz[1] ; clk_div:clkdiv_inst|count_1Mhz[4] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 1.000 ; -0.048 ; 1.865 ;; -0.805 ; clk_div:clkdiv_inst|count_1Mhz[0] ; clk_div:clkdiv_inst|count_1Mhz[4] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 1.000 ; -0.048 ; 1.775 ;; -0.784 ; clk_div:clkdiv_inst|count_1Mhz[3] ; clk_div:clkdiv_inst|count_1Mhz[4] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 1.000 ; -0.048 ; 1.754 ;; -0.775 ; clk_div:clkdiv_inst|count_1Mhz[0] ; clk_div:clkdiv_inst|count_1Mhz[3] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 1.000 ; -0.048 ; 1.745 ;; -0.763 ; clk_div:clkdiv_inst|count_1Mhz[1] ; clk_div:clkdiv_inst|count_1Mhz[2] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 1.000 ; -0.048 ; 1.733 ;; -0.744 ; clk_div:clkdiv_inst|count_1Mhz[1] ; clk_div:clkdiv_inst|count_1Mhz[3] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 1.000 ; -0.048 ; 1.714 ;; -0.709 ; clk_div:clkdiv_inst|count_1Mhz[4] ; clk_div:clkdiv_inst|count_1Mhz[3] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 1.000 ; -0.048 ; 1.679 ;; -0.709 ; clk_div:clkdiv_inst|count_1Mhz[4] ; clk_div:clkdiv_inst|count_1Mhz[2] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 1.000 ; -0.048 ; 1.679 ;; -0.709 ; clk_div:clkdiv_inst|count_1Mhz[4] ; clk_div:clkdiv_inst|count_1Mhz[1] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 1.000 ; -0.048 ; 1.679 ;; -0.709 ; clk_div:clkdiv_inst|count_1Mhz[4] ; clk_div:clkdiv_inst|count_1Mhz[0] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 1.000 ; -0.048 ; 1.679 ;; -0.704 ; clk_div:clkdiv_inst|count_1Mhz[4] ; clk_div:clkdiv_inst|count_1Mhz[4] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 1.000 ; -0.043 ; 1.679 ;; -0.691 ; clk_div:clkdiv_inst|count_1Mhz[2] ; clk_div:clkdiv_inst|count_1Mhz[4] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 1.000 ; -0.048 ; 1.661 ;; -0.673 ; clk_div:clkdiv_inst|count_1Mhz[0] ; clk_div:clkdiv_inst|count_1Mhz[2] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 1.000 ; -0.048 ; 1.643 ;; -0.646 ; clk_div:clkdiv_inst|count_1Mhz[2] ; clk_div:clkdiv_inst|count_1Mhz[3] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 1.000 ; -0.048 ; 1.616 ;; -0.643 ; clk_div:clkdiv_inst|count_1Mhz[0] ; clk_div:clkdiv_inst|count_1Mhz[1] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 1.000 ; -0.048 ; 1.613 ;; -0.544 ; clk_div:clkdiv_inst|count_1Mhz[3] ; clk_div:clkdiv_inst|count_1Mhz[2] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 1.000 ; -0.048 ; 1.514 ;; -0.544 ; clk_div:clkdiv_inst|count_1Mhz[3] ; clk_div:clkdiv_inst|count_1Mhz[1] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 1.000 ; -0.048 ; 1.514 ;; -0.544 ; clk_div:clkdiv_inst|count_1Mhz[3] ; clk_div:clkdiv_inst|count_1Mhz[0] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 1.000 ; -0.048 ; 1.514 ;; -0.539 ; clk_div:clkdiv_inst|count_1Mhz[3] ; clk_div:clkdiv_inst|count_1Mhz[3] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 1.000 ; -0.043 ; 1.514 ;; -0.175 ; clk_div:clkdiv_inst|count_1Mhz[2] ; clk_div:clkdiv_inst|count_1Mhz[2] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 1.000 ; -0.043 ; 1.150 ;; -0.155 ; clk_div:clkdiv_inst|count_1Mhz[0] ; clk_div:clkdiv_inst|count_1Mhz[0] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 1.000 ; -0.043 ; 1.130 ;; -0.136 ; clk_div:clkdiv_inst|count_1Mhz[1] ; clk_div:clkdiv_inst|count_1Mhz[1] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 1.000 ; -0.043 ; 1.111 ;; -0.113 ; clk_div:clkdiv_inst|count_1Mhz[2] ; clk_div:clkdiv_inst|clock_1Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 1.000 ; -0.048 ; 1.083 ;; -0.007 ; clk_div:clkdiv_inst|count_1Mhz[4] ; clk_div:clkdiv_inst|clock_1Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 1.000 ; -0.048 ; 0.977 ;; 0.158 ; clk_div:clkdiv_inst|count_1Mhz[3] ; clk_div:clkdiv_inst|clock_1Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 1.000 ; -0.048 ; 0.812 ;+--------+-----------------------------------+------------------------------------+-------------------------------------+-------------------------------------+--------------+------------+------------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Setup: 'clk_div:clkdiv_inst|clock_1Mhz_int' ;+--------+--------------------------------------+--------------------------------------+--------------------------------------+------------------------------------+--------------+------------+------------+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;+--------+--------------------------------------+--------------------------------------+--------------------------------------+------------------------------------+--------------+------------+------------+; -0.665 ; clk_div:clkdiv_inst|count_100Khz[0] ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_1Mhz_int ; clk_div:clkdiv_inst|clock_1Mhz_int ; 1.000 ; -0.046 ; 1.637 ;; -0.358 ; clk_div:clkdiv_inst|count_100Khz[2] ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_1Mhz_int ; clk_div:clkdiv_inst|clock_1Mhz_int ; 1.000 ; -0.046 ; 1.330 ;; -0.209 ; clk_div:clkdiv_inst|count_100Khz[1] ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_1Mhz_int ; clk_div:clkdiv_inst|clock_1Mhz_int ; 1.000 ; -0.046 ; 1.181 ;; -0.164 ; clk_div:clkdiv_inst|count_100Khz[0] ; clk_div:clkdiv_inst|count_100Khz[2] ; clk_div:clkdiv_inst|clock_1Mhz_int ; clk_div:clkdiv_inst|clock_1Mhz_int ; 1.000 ; -0.046 ; 1.136 ;; -0.116 ; clk_div:clkdiv_inst|count_100Khz[1] ; clk_div:clkdiv_inst|count_100Khz[0] ; clk_div:clkdiv_inst|clock_1Mhz_int ; clk_div:clkdiv_inst|clock_1Mhz_int ; 1.000 ; -0.046 ; 1.088 ;; 0.011 ; clk_div:clkdiv_inst|count_100Khz[2] ; clk_div:clkdiv_inst|count_100Khz[0] ; clk_div:clkdiv_inst|clock_1Mhz_int ; clk_div:clkdiv_inst|clock_1Mhz_int ; 1.000 ; -0.046 ; 0.961 ;; 0.136 ; clk_div:clkdiv_inst|count_100Khz[0] ; clk_div:clkdiv_inst|count_100Khz[1] ; clk_div:clkdiv_inst|clock_1Mhz_int ; clk_div:clkdiv_inst|clock_1Mhz_int ; 1.000 ; -0.046 ; 0.836 ;; 0.152 ; clk_div:clkdiv_inst|count_100Khz[1] ; clk_div:clkdiv_inst|count_100Khz[2] ; clk_div:clkdiv_inst|clock_1Mhz_int ; clk_div:clkdiv_inst|clock_1Mhz_int ; 1.000 ; -0.046 ; 0.820 ;; 0.210 ; clk_div:clkdiv_inst|count_100Khz[2] ; clk_div:clkdiv_inst|count_100Khz[2] ; clk_div:clkdiv_inst|clock_1Mhz_int ; clk_div:clkdiv_inst|clock_1Mhz_int ; 1.000 ; -0.043 ; 0.765 ;; 0.210 ; clk_div:clkdiv_inst|count_100Khz[0] ; clk_div:clkdiv_inst|count_100Khz[0] ; clk_div:clkdiv_inst|clock_1Mhz_int ; clk_div:clkdiv_inst|clock_1Mhz_int ; 1.000 ; -0.043 ; 0.765 ;; 0.210 ; clk_div:clkdiv_inst|count_100Khz[1] ; clk_div:clkdiv_inst|count_100Khz[1] ; clk_div:clkdiv_inst|clock_1Mhz_int ; clk_div:clkdiv_inst|clock_1Mhz_int ; 1.000 ; -0.043 ; 0.765 ;; 0.303 ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_1Mhz_int ; 0.500 ; 2.160 ; 2.607 ;; 0.859 ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_1Mhz_int ; 1.000 ; 2.160 ; 2.551 ;+--------+--------------------------------------+--------------------------------------+--------------------------------------+------------------------------------+--------------+------------+------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Setup: 'clk_div:clkdiv_inst|clock_10Khz_int' ;+--------+------------------------------------+------------------------------------+-------------------------------------+-------------------------------------+--------------+------------+------------+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;+--------+------------------------------------+------------------------------------+-------------------------------------+-------------------------------------+--------------+------------+------------+; -0.522 ; clk_div:clkdiv_inst|count_1Khz[0] ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; 1.000 ; -0.045 ; 1.495 ;; -0.343 ; clk_div:clkdiv_inst|count_1Khz[2] ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; 1.000 ; -0.045 ; 1.316 ;; -0.206 ; clk_div:clkdiv_inst|count_1Khz[1] ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; 1.000 ; -0.045 ; 1.179 ;; -0.182 ; clk_div:clkdiv_inst|count_1Khz[1] ; clk_div:clkdiv_inst|count_1Khz[0] ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; 1.000 ; -0.045 ; 1.155 ;; -0.171 ; clk_div:clkdiv_inst|count_1Khz[0] ; clk_div:clkdiv_inst|count_1Khz[2] ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; 1.000 ; -0.045 ; 1.144 ;; -0.145 ; clk_div:clkdiv_inst|count_1Khz[2] ; clk_div:clkdiv_inst|count_1Khz[0] ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; 1.000 ; -0.045 ; 1.118 ;; 0.146 ; clk_div:clkdiv_inst|count_1Khz[0] ; clk_div:clkdiv_inst|count_1Khz[1] ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; 1.000 ; -0.045 ; 0.827 ;; 0.154 ; clk_div:clkdiv_inst|count_1Khz[1] ; clk_div:clkdiv_inst|count_1Khz[2] ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; 1.000 ; -0.045 ; 0.819 ;; 0.176 ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; 0.500 ; 1.355 ; 1.929 ;; 0.210 ; clk_div:clkdiv_inst|count_1Khz[2] ; clk_div:clkdiv_inst|count_1Khz[2] ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; 1.000 ; -0.043 ; 0.765 ;; 0.210 ; clk_div:clkdiv_inst|count_1Khz[0] ; clk_div:clkdiv_inst|count_1Khz[0] ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; 1.000 ; -0.043 ; 0.765 ;; 0.210 ; clk_div:clkdiv_inst|count_1Khz[1] ; clk_div:clkdiv_inst|count_1Khz[1] ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; 1.000 ; -0.043 ; 0.765 ;; 0.728 ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; 1.000 ; 1.355 ; 1.877 ;+--------+------------------------------------+------------------------------------+-------------------------------------+-------------------------------------+--------------+------------+------------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Setup: 'clk_div:clkdiv_inst|clock_100Khz_int' ;+--------+-------------------------------------+-------------------------------------+--------------------------------------+--------------------------------------+--------------+------------+------------+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;+--------+-------------------------------------+-------------------------------------+--------------------------------------+--------------------------------------+--------------+------------+------------+; -0.506 ; clk_div:clkdiv_inst|count_10Khz[0] ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; 1.000 ; -0.047 ; 1.477 ;; -0.346 ; clk_div:clkdiv_inst|count_10Khz[2] ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; 1.000 ; -0.047 ; 1.317 ;; -0.210 ; clk_div:clkdiv_inst|count_10Khz[1] ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; 1.000 ; -0.047 ; 1.181 ;; -0.170 ; clk_div:clkdiv_inst|count_10Khz[2] ; clk_div:clkdiv_inst|count_10Khz[0] ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; 1.000 ; -0.047 ; 1.141 ;; -0.148 ; clk_div:clkdiv_inst|count_10Khz[1] ; clk_div:clkdiv_inst|count_10Khz[2] ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; 1.000 ; -0.047 ; 1.119 ;; -0.052 ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; 0.500 ; 0.864 ; 1.666 ;; -0.007 ; clk_div:clkdiv_inst|count_10Khz[0] ; clk_div:clkdiv_inst|count_10Khz[1] ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; 1.000 ; -0.047 ; 0.978 ;; -0.007 ; clk_div:clkdiv_inst|count_10Khz[0] ; clk_div:clkdiv_inst|count_10Khz[2] ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; 1.000 ; -0.047 ; 0.978 ;; 0.157 ; clk_div:clkdiv_inst|count_10Khz[1] ; clk_div:clkdiv_inst|count_10Khz[0] ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; 1.000 ; -0.047 ; 0.814 ;; 0.210 ; clk_div:clkdiv_inst|count_10Khz[2] ; clk_div:clkdiv_inst|count_10Khz[2] ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; 1.000 ; -0.043 ; 0.765 ;; 0.210 ; clk_div:clkdiv_inst|count_10Khz[0] ; clk_div:clkdiv_inst|count_10Khz[0] ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; 1.000 ; -0.043 ; 0.765 ;; 0.210 ; clk_div:clkdiv_inst|count_10Khz[1] ; clk_div:clkdiv_inst|count_10Khz[1] ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; 1.000 ; -0.043 ; 0.765 ;; 0.527 ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; 1.000 ; 0.864 ; 1.587 ;+--------+-------------------------------------+-------------------------------------+--------------------------------------+--------------------------------------+--------------+------------+------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Setup: 'clk_div:clkdiv_inst|clock_1Khz_int' ;+--------+-------------------------------------+-------------------------------------+------------------------------------+------------------------------------+--------------+------------+------------+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;+--------+-------------------------------------+-------------------------------------+------------------------------------+------------------------------------+--------------+------------+------------+; -0.320 ; clk_div:clkdiv_inst|count_100hz[0] ; clk_div:clkdiv_inst|clock_100hz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; 1.000 ; -0.047 ; 1.291 ;; -0.165 ; clk_div:clkdiv_inst|count_100hz[0] ; clk_div:clkdiv_inst|count_100hz[2] ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; 1.000 ; -0.047 ; 1.136 ;; -0.153 ; clk_div:clkdiv_inst|count_100hz[2] ; clk_div:clkdiv_inst|clock_100hz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; 1.000 ; -0.047 ; 1.124 ;; -0.115 ; clk_div:clkdiv_inst|count_100hz[1] ; clk_div:clkdiv_inst|count_100hz[0] ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; 1.000 ; -0.047 ; 1.086 ;; 0.137 ; clk_div:clkdiv_inst|count_100hz[0] ; clk_div:clkdiv_inst|count_100hz[1] ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; 1.000 ; -0.047 ; 0.834 ;; 0.150 ; clk_div:clkdiv_inst|count_100hz[1] ; clk_div:clkdiv_inst|clock_100hz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; 1.000 ; -0.047 ; 0.821 ;; 0.150 ; clk_div:clkdiv_inst|count_100hz[1] ; clk_div:clkdiv_inst|count_100hz[2] ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; 1.000 ; -0.047 ; 0.821 ;; 0.161 ; clk_div:clkdiv_inst|count_100hz[2] ; clk_div:clkdiv_inst|count_100hz[0] ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; 1.000 ; -0.047 ; 0.810 ;; 0.210 ; clk_div:clkdiv_inst|count_100hz[2] ; clk_div:clkdiv_inst|count_100hz[2] ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; 1.000 ; -0.043 ; 0.765 ;; 0.210 ; clk_div:clkdiv_inst|count_100hz[0] ; clk_div:clkdiv_inst|count_100hz[0] ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; 1.000 ; -0.043 ; 0.765 ;; 0.210 ; clk_div:clkdiv_inst|count_100hz[1] ; clk_div:clkdiv_inst|count_100hz[1] ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; 1.000 ; -0.043 ; 0.765 ;; 0.210 ; clk_div:clkdiv_inst|clock_100hz_int ; clk_div:clkdiv_inst|clock_100hz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; 1.000 ; -0.043 ; 0.765 ;+--------+-------------------------------------+-------------------------------------+------------------------------------+------------------------------------+--------------+------------+------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Hold: 'SW[15]' ;+--------+--------------------------------+---------------------------------------------------------------------------------------------------------------+-----------------------+-------------+--------------+------------+------------+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;+--------+--------------------------------+---------------------------------------------------------------------------------------------------------------+-----------------------+-------------+--------------+------------+------------+; -5.753 ; \random:rand_temp[11] ; T80se:z80_inst|T80:u0|IR[3] ; CLOCK_50 ; SW[15] ; 0.000 ; 6.885 ; 1.358 ;; -5.606 ; \random:rand_temp[11] ; T80se:z80_inst|DI_Reg[3] ; CLOCK_50 ; SW[15] ; 0.000 ; 6.882 ; 1.502 ;; -5.212 ; \random:rand_temp[12] ; T80se:z80_inst|DI_Reg[4] ; CLOCK_50 ; SW[15] ; 0.000 ; 6.885 ; 1.899 ;; -5.211 ; \random:rand_temp[12] ; T80se:z80_inst|T80:u0|IR[4] ; CLOCK_50 ; SW[15] ; 0.000 ; 6.885 ; 1.900 ;; -4.767 ; \random:rand_temp[1] ; T80se:z80_inst|T80:u0|IR[1] ; CLOCK_50 ; SW[15] ; 0.000 ; 6.889 ; 2.348 ;; -4.757 ; \random:rand_temp[14] ; T80se:z80_inst|DI_Reg[6] ; CLOCK_50 ; SW[15] ; 0.000 ; 6.882 ; 2.351 ;; -4.725 ; \random:rand_temp[1] ; T80se:z80_inst|DI_Reg[1] ; CLOCK_50 ; SW[15] ; 0.000 ; 6.882 ; 2.383 ;; -4.614 ; \random:rand_temp[14] ; T80se:z80_inst|T80:u0|IR[6] ; CLOCK_50 ; SW[15] ; 0.000 ; 6.884 ; 2.496 ;; -4.541 ; \random:rand_temp[13] ; T80se:z80_inst|DI_Reg[5] ; CLOCK_50 ; SW[15] ; 0.000 ; 6.882 ; 2.567 ;; -4.484 ; T80se:z80_inst|MREQ_n ; T80se:z80_inst|DI_Reg[2] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.826 ; 5.790 ;; -4.454 ; T80se:z80_inst|MREQ_n ; T80se:z80_inst|T80:u0|IR[2] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.833 ; 5.827 ;; -4.401 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDR_sig[4] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.833 ; 5.880 ;; -4.398 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDR_sig[0] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.833 ; 5.883 ;; -4.381 ; T80se:z80_inst|MREQ_n ; T80se:z80_inst|T80:u0|IR[1] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.833 ; 5.900 ;; -4.380 ; T80se:z80_inst|MREQ_n ; T80se:z80_inst|T80:u0|IR[3] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.834 ; 5.902 ;; -4.366 ; \random:rand_temp[13] ; T80se:z80_inst|T80:u0|IR[5] ; CLOCK_50 ; SW[15] ; 0.000 ; 6.885 ; 2.745 ;; -4.365 ; T80se:z80_inst|MREQ_n ; T80se:z80_inst|T80:u0|IR[0] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.833 ; 5.916 ;; -4.364 ; T80se:z80_inst|MREQ_n ; T80se:z80_inst|T80:u0|IR[7] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.822 ; 5.906 ;; -4.357 ; T80se:z80_inst|MREQ_n ; T80se:z80_inst|DI_Reg[1] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.826 ; 5.917 ;; -4.357 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDR_sig[9] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.831 ; 5.922 ;; -4.357 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDR_sig[11] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.831 ; 5.922 ;; -4.355 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDR_sig[14] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.831 ; 5.924 ;; -4.355 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDR_sig[15] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.831 ; 5.924 ;; -4.354 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDR_sig[13] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.831 ; 5.925 ;; -4.353 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDR_sig[8] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.831 ; 5.926 ;; -4.351 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDR_sig[10] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.831 ; 5.928 ;; -4.350 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDR_sig[12] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.831 ; 5.929 ;; -4.311 ; T80se:z80_inst|MREQ_n ; T80se:z80_inst|DI_Reg[4] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.834 ; 5.971 ;; -4.310 ; T80se:z80_inst|MREQ_n ; T80se:z80_inst|T80:u0|IR[4] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.834 ; 5.972 ;; -4.293 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDR_sig[2] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.829 ; 5.984 ;; -4.291 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDR_sig[7] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.829 ; 5.986 ;; -4.289 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDR_sig[3] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.829 ; 5.988 ;; -4.288 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDR_sig[5] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.829 ; 5.989 ;; -4.285 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDR_sig[1] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.829 ; 5.992 ;; -4.285 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDR_sig[6] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.829 ; 5.992 ;; -4.275 ; T80se:z80_inst|MREQ_n ; T80se:z80_inst|DI_Reg[5] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.831 ; 6.004 ;; -4.237 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER0_sig[0] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.823 ; 6.034 ;; -4.237 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER0_sig[1] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.823 ; 6.034 ;; -4.237 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER0_sig[2] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.823 ; 6.034 ;; -4.237 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER0_sig[3] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.823 ; 6.034 ;; -4.237 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER1_sig[0] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.823 ; 6.034 ;; -4.237 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER1_sig[1] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.823 ; 6.034 ;; -4.237 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER1_sig[2] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.823 ; 6.034 ;; -4.237 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER1_sig[3] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.823 ; 6.034 ;; -4.233 ; T80se:z80_inst|MREQ_n ; T80se:z80_inst|DI_Reg[3] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.831 ; 6.046 ;; -4.233 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDG_sig[0] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.833 ; 6.048 ;; -4.233 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDG_sig[1] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.833 ; 6.048 ;; -4.233 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDG_sig[2] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.833 ; 6.048 ;; -4.233 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDG_sig[3] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.833 ; 6.048 ;; -4.233 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDG_sig[4] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.833 ; 6.048 ;; -4.233 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDG_sig[5] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.833 ; 6.048 ;; -4.233 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDG_sig[6] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.833 ; 6.048 ;; -4.233 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDG_sig[7] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.833 ; 6.048 ;; -4.162 ; T80se:z80_inst|MREQ_n ; T80se:z80_inst|T80:u0|IR[6] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.833 ; 6.119 ;; -4.156 ; T80se:z80_inst|MREQ_n ; T80se:z80_inst|T80:u0|IR[5] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.834 ; 6.126 ;; -4.124 ; T80se:z80_inst|MREQ_n ; T80se:z80_inst|DI_Reg[7] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.826 ; 6.150 ;; -4.118 ; LCD:lcd_inst|char_count_sig[0] ; next_char_sig[2] ; CLOCK_50 ; SW[15] ; 0.000 ; 6.874 ; 2.982 ;; -4.116 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER6_sig[0] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.838 ; 6.170 ;; -4.116 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER6_sig[1] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.838 ; 6.170 ;; -4.116 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER6_sig[2] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.838 ; 6.170 ;; -4.116 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER6_sig[3] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.838 ; 6.170 ;; -4.116 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER7_sig[0] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.838 ; 6.170 ;; -4.116 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER7_sig[1] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.838 ; 6.170 ;; -4.116 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER7_sig[2] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.838 ; 6.170 ;; -4.116 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER7_sig[3] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.838 ; 6.170 ;; -4.112 ; T80se:z80_inst|MREQ_n ; T80se:z80_inst|DI_Reg[0] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.831 ; 6.167 ;; -4.106 ; T80se:z80_inst|MREQ_n ; T80se:z80_inst|DI_Reg[6] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.831 ; 6.173 ;; -4.073 ; LCD:lcd_inst|char_count_sig[0] ; next_char_sig[6] ; CLOCK_50 ; SW[15] ; 0.000 ; 6.873 ; 3.026 ;; -4.037 ; \random:rand_temp[4] ; T80se:z80_inst|DI_Reg[4] ; CLOCK_50 ; SW[15] ; 0.000 ; 6.890 ; 3.079 ;; -4.012 ; \random:rand_temp[4] ; T80se:z80_inst|T80:u0|IR[4] ; CLOCK_50 ; SW[15] ; 0.000 ; 6.890 ; 3.104 ;; -4.007 ; T80se:z80_inst|MREQ_n ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a6~porta_datain_reg0 ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 10.154 ; 6.631 ;; -4.006 ; T80se:z80_inst|MREQ_n ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a6~porta_address_reg0 ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 10.148 ; 6.626 ;; -4.006 ; T80se:z80_inst|MREQ_n ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a6~porta_we_reg ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 10.148 ; 6.626 ;; -4.001 ; LCD:lcd_inst|char_count_sig[1] ; next_char_sig[4] ; CLOCK_50 ; SW[15] ; 0.000 ; 6.889 ; 3.114 ;; -4.000 ; T80se:z80_inst|MREQ_n ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a0~porta_datain_reg0 ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 10.157 ; 6.641 ;; -3.999 ; T80se:z80_inst|MREQ_n ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a0~porta_address_reg0 ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 10.151 ; 6.636 ;; -3.999 ; T80se:z80_inst|MREQ_n ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a0~porta_we_reg ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 10.151 ; 6.636 ;; -3.995 ; LCD:lcd_inst|char_count_sig[0] ; next_char_sig[7] ; CLOCK_50 ; SW[15] ; 0.000 ; 6.876 ; 3.107 ;; -3.993 ; LCD:lcd_inst|char_count_sig[1] ; next_char_sig[1] ; CLOCK_50 ; SW[15] ; 0.000 ; 6.891 ; 3.124 ;; -3.990 ; T80se:z80_inst|MREQ_n ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a1~porta_datain_reg0 ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 10.169 ; 6.663 ;; -3.989 ; T80se:z80_inst|MREQ_n ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a1~porta_address_reg0 ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 10.163 ; 6.658 ;; -3.989 ; T80se:z80_inst|MREQ_n ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a1~porta_we_reg ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 10.163 ; 6.658 ;; -3.985 ; LCD:lcd_inst|char_count_sig[3] ; next_char_sig[3] ; CLOCK_50 ; SW[15] ; 0.000 ; 6.890 ; 3.131 ;; -3.984 ; T80se:z80_inst|MREQ_n ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a3~porta_datain_reg0 ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 10.150 ; 6.650 ;; -3.983 ; T80se:z80_inst|MREQ_n ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a3~porta_address_reg0 ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 10.144 ; 6.645 ;; -3.983 ; T80se:z80_inst|MREQ_n ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a3~porta_we_reg ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 10.144 ; 6.645 ;; -3.981 ; LCD:lcd_inst|char_count_sig[1] ; next_char_sig[7] ; CLOCK_50 ; SW[15] ; 0.000 ; 6.876 ; 3.121 ;; -3.980 ; ps2_ascii_reg1[5] ; ps2_ascii_reg[5] ; CLOCK_50 ; SW[15] ; 0.000 ; 6.884 ; 3.130 ;; -3.979 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER5_sig[0] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.812 ; 6.281 ;; -3.979 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER5_sig[1] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.812 ; 6.281 ;; -3.979 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER5_sig[2] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.812 ; 6.281 ;; -3.979 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER5_sig[3] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.812 ; 6.281 ;; -3.976 ; LCD:lcd_inst|char_count_sig[1] ; next_char_sig[6] ; CLOCK_50 ; SW[15] ; 0.000 ; 6.873 ; 3.123 ;; -3.971 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER3_sig[0] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.821 ; 6.298 ;; -3.971 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER3_sig[1] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.821 ; 6.298 ;; -3.971 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER3_sig[2] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.821 ; 6.298 ;; -3.971 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER3_sig[3] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.821 ; 6.298 ;; -3.970 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER4_sig[0] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.820 ; 6.298 ;; -3.970 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER4_sig[1] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.820 ; 6.298 ;; -3.970 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER4_sig[2] ; T80se:z80_inst|MREQ_n ; SW[15] ; 0.000 ; 9.820 ; 6.298 ;+--------+--------------------------------+---------------------------------------------------------------------------------------------------------------+-----------------------+-------------+--------------+------------+------------++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Hold: 'clk_div:clkdiv_inst|clock_100Hz' ;+--------+--------------------------------+---------------------------------------------------------------------------------------------------------------+-----------------------+---------------------------------+--------------+------------+------------+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;+--------+--------------------------------+---------------------------------------------------------------------------------------------------------------+-----------------------+---------------------------------+--------------+------------+------------+; -1.638 ; \random:rand_temp[11] ; T80se:z80_inst|T80:u0|IR[3] ; CLOCK_50 ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 2.780 ; 1.358 ;; -1.491 ; \random:rand_temp[11] ; T80se:z80_inst|DI_Reg[3] ; CLOCK_50 ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 2.777 ; 1.502 ;; -1.097 ; \random:rand_temp[12] ; T80se:z80_inst|DI_Reg[4] ; CLOCK_50 ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 2.780 ; 1.899 ;; -1.096 ; \random:rand_temp[12] ; T80se:z80_inst|T80:u0|IR[4] ; CLOCK_50 ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 2.780 ; 1.900 ;; -0.652 ; \random:rand_temp[1] ; T80se:z80_inst|T80:u0|IR[1] ; CLOCK_50 ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 2.784 ; 2.348 ;; -0.642 ; \random:rand_temp[14] ; T80se:z80_inst|DI_Reg[6] ; CLOCK_50 ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 2.777 ; 2.351 ;; -0.610 ; \random:rand_temp[1] ; T80se:z80_inst|DI_Reg[1] ; CLOCK_50 ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 2.777 ; 2.383 ;; -0.499 ; \random:rand_temp[14] ; T80se:z80_inst|T80:u0|IR[6] ; CLOCK_50 ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 2.779 ; 2.496 ;; -0.426 ; \random:rand_temp[13] ; T80se:z80_inst|DI_Reg[5] ; CLOCK_50 ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 2.777 ; 2.567 ;; -0.369 ; T80se:z80_inst|MREQ_n ; T80se:z80_inst|DI_Reg[2] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.721 ; 5.790 ;; -0.339 ; T80se:z80_inst|MREQ_n ; T80se:z80_inst|T80:u0|IR[2] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.728 ; 5.827 ;; -0.286 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDR_sig[4] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.728 ; 5.880 ;; -0.283 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDR_sig[0] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.728 ; 5.883 ;; -0.266 ; T80se:z80_inst|MREQ_n ; T80se:z80_inst|T80:u0|IR[1] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.728 ; 5.900 ;; -0.265 ; T80se:z80_inst|MREQ_n ; T80se:z80_inst|T80:u0|IR[3] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.729 ; 5.902 ;; -0.251 ; \random:rand_temp[13] ; T80se:z80_inst|T80:u0|IR[5] ; CLOCK_50 ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 2.780 ; 2.745 ;; -0.250 ; T80se:z80_inst|MREQ_n ; T80se:z80_inst|T80:u0|IR[0] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.728 ; 5.916 ;; -0.249 ; T80se:z80_inst|MREQ_n ; T80se:z80_inst|T80:u0|IR[7] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.717 ; 5.906 ;; -0.242 ; T80se:z80_inst|MREQ_n ; T80se:z80_inst|DI_Reg[1] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.721 ; 5.917 ;; -0.242 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDR_sig[9] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.726 ; 5.922 ;; -0.242 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDR_sig[11] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.726 ; 5.922 ;; -0.240 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDR_sig[14] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.726 ; 5.924 ;; -0.240 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDR_sig[15] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.726 ; 5.924 ;; -0.239 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDR_sig[13] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.726 ; 5.925 ;; -0.238 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDR_sig[8] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.726 ; 5.926 ;; -0.236 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDR_sig[10] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.726 ; 5.928 ;; -0.235 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDR_sig[12] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.726 ; 5.929 ;; -0.196 ; T80se:z80_inst|MREQ_n ; T80se:z80_inst|DI_Reg[4] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.729 ; 5.971 ;; -0.195 ; T80se:z80_inst|MREQ_n ; T80se:z80_inst|T80:u0|IR[4] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.729 ; 5.972 ;; -0.178 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDR_sig[2] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.724 ; 5.984 ;; -0.176 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDR_sig[7] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.724 ; 5.986 ;; -0.174 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDR_sig[3] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.724 ; 5.988 ;; -0.173 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDR_sig[5] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.724 ; 5.989 ;; -0.170 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDR_sig[1] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.724 ; 5.992 ;; -0.170 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDR_sig[6] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.724 ; 5.992 ;; -0.160 ; T80se:z80_inst|MREQ_n ; T80se:z80_inst|DI_Reg[5] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.726 ; 6.004 ;; -0.122 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER0_sig[0] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.718 ; 6.034 ;; -0.122 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER0_sig[1] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.718 ; 6.034 ;; -0.122 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER0_sig[2] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.718 ; 6.034 ;; -0.122 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER0_sig[3] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.718 ; 6.034 ;; -0.122 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER1_sig[0] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.718 ; 6.034 ;; -0.122 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER1_sig[1] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.718 ; 6.034 ;; -0.122 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER1_sig[2] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.718 ; 6.034 ;; -0.122 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER1_sig[3] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.718 ; 6.034 ;; -0.118 ; T80se:z80_inst|MREQ_n ; T80se:z80_inst|DI_Reg[3] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.726 ; 6.046 ;; -0.118 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDG_sig[0] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.728 ; 6.048 ;; -0.118 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDG_sig[1] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.728 ; 6.048 ;; -0.118 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDG_sig[2] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.728 ; 6.048 ;; -0.118 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDG_sig[3] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.728 ; 6.048 ;; -0.118 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDG_sig[4] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.728 ; 6.048 ;; -0.118 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDG_sig[5] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.728 ; 6.048 ;; -0.118 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDG_sig[6] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.728 ; 6.048 ;; -0.118 ; T80se:z80_inst|MREQ_n ; \pinout_process:LEDG_sig[7] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.728 ; 6.048 ;; -0.047 ; T80se:z80_inst|MREQ_n ; T80se:z80_inst|T80:u0|IR[6] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.728 ; 6.119 ;; -0.041 ; T80se:z80_inst|MREQ_n ; T80se:z80_inst|T80:u0|IR[5] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.729 ; 6.126 ;; -0.009 ; T80se:z80_inst|MREQ_n ; T80se:z80_inst|DI_Reg[7] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.721 ; 6.150 ;; -0.003 ; LCD:lcd_inst|char_count_sig[0] ; next_char_sig[2] ; CLOCK_50 ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 2.769 ; 2.982 ;; -0.001 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER6_sig[0] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.733 ; 6.170 ;; -0.001 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER6_sig[1] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.733 ; 6.170 ;; -0.001 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER6_sig[2] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.733 ; 6.170 ;; -0.001 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER6_sig[3] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.733 ; 6.170 ;; -0.001 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER7_sig[0] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.733 ; 6.170 ;; -0.001 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER7_sig[1] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.733 ; 6.170 ;; -0.001 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER7_sig[2] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.733 ; 6.170 ;; -0.001 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER7_sig[3] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.733 ; 6.170 ;; 0.003 ; T80se:z80_inst|MREQ_n ; T80se:z80_inst|DI_Reg[0] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.726 ; 6.167 ;; 0.009 ; T80se:z80_inst|MREQ_n ; T80se:z80_inst|DI_Reg[6] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.726 ; 6.173 ;; 0.042 ; LCD:lcd_inst|char_count_sig[0] ; next_char_sig[6] ; CLOCK_50 ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 2.768 ; 3.026 ;; 0.078 ; \random:rand_temp[4] ; T80se:z80_inst|DI_Reg[4] ; CLOCK_50 ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 2.785 ; 3.079 ;; 0.103 ; \random:rand_temp[4] ; T80se:z80_inst|T80:u0|IR[4] ; CLOCK_50 ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 2.785 ; 3.104 ;; 0.108 ; T80se:z80_inst|MREQ_n ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a6~porta_datain_reg0 ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 6.049 ; 6.631 ;; 0.109 ; T80se:z80_inst|MREQ_n ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a6~porta_address_reg0 ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 6.043 ; 6.626 ;; 0.109 ; T80se:z80_inst|MREQ_n ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a6~porta_we_reg ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 6.043 ; 6.626 ;; 0.114 ; LCD:lcd_inst|char_count_sig[1] ; next_char_sig[4] ; CLOCK_50 ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 2.784 ; 3.114 ;; 0.115 ; T80se:z80_inst|MREQ_n ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a0~porta_datain_reg0 ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 6.052 ; 6.641 ;; 0.116 ; T80se:z80_inst|MREQ_n ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a0~porta_address_reg0 ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 6.046 ; 6.636 ;; 0.116 ; T80se:z80_inst|MREQ_n ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a0~porta_we_reg ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 6.046 ; 6.636 ;; 0.120 ; LCD:lcd_inst|char_count_sig[0] ; next_char_sig[7] ; CLOCK_50 ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 2.771 ; 3.107 ;; 0.122 ; LCD:lcd_inst|char_count_sig[1] ; next_char_sig[1] ; CLOCK_50 ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 2.786 ; 3.124 ;; 0.125 ; T80se:z80_inst|MREQ_n ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a1~porta_datain_reg0 ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 6.064 ; 6.663 ;; 0.126 ; T80se:z80_inst|MREQ_n ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a1~porta_address_reg0 ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 6.058 ; 6.658 ;; 0.126 ; T80se:z80_inst|MREQ_n ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a1~porta_we_reg ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 6.058 ; 6.658 ;; 0.130 ; LCD:lcd_inst|char_count_sig[3] ; next_char_sig[3] ; CLOCK_50 ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 2.785 ; 3.131 ;; 0.131 ; T80se:z80_inst|MREQ_n ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a3~porta_datain_reg0 ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 6.045 ; 6.650 ;; 0.132 ; T80se:z80_inst|MREQ_n ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a3~porta_address_reg0 ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 6.039 ; 6.645 ;; 0.132 ; T80se:z80_inst|MREQ_n ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a3~porta_we_reg ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 6.039 ; 6.645 ;; 0.134 ; LCD:lcd_inst|char_count_sig[1] ; next_char_sig[7] ; CLOCK_50 ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 2.771 ; 3.121 ;; 0.135 ; ps2_ascii_reg1[5] ; ps2_ascii_reg[5] ; CLOCK_50 ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 2.779 ; 3.130 ;; 0.136 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER5_sig[0] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.707 ; 6.281 ;; 0.136 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER5_sig[1] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.707 ; 6.281 ;; 0.136 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER5_sig[2] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.707 ; 6.281 ;; 0.136 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER5_sig[3] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.707 ; 6.281 ;; 0.139 ; LCD:lcd_inst|char_count_sig[1] ; next_char_sig[6] ; CLOCK_50 ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 2.768 ; 3.123 ;; 0.144 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER3_sig[0] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.716 ; 6.298 ;; 0.144 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER3_sig[1] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.716 ; 6.298 ;; 0.144 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER3_sig[2] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.716 ; 6.298 ;; 0.144 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER3_sig[3] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.716 ; 6.298 ;; 0.145 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER4_sig[0] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.715 ; 6.298 ;; 0.145 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER4_sig[1] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.715 ; 6.298 ;; 0.145 ; T80se:z80_inst|MREQ_n ; \pinout_process:NUMBER4_sig[2] ; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 0.000 ; 5.715 ; 6.298 ;+--------+--------------------------------+---------------------------------------------------------------------------------------------------------------+-----------------------+---------------------------------+--------------+------------+------------++----------------------------------------------------------------------------------------------------------------------------------------------------------+; Hold: 'T80se:z80_inst|MREQ_n' ;+--------+-----------------------------+----------------+---------------------------------+-----------------------+--------------+------------+------------+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;+--------+-----------------------------+----------------+---------------------------------+-----------------------+--------------+------------+------------+; -1.628 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[18][2] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 4.585 ; 2.477 ;; -1.457 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[18][3] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 4.517 ; 2.580 ;; -1.433 ; T80se:z80_inst|T80:u0|DO[1] ; lcdvram[18][1] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 4.366 ; 2.453 ;; -1.354 ; T80se:z80_inst|T80:u0|DO[6] ; lcdvram[18][6] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 4.585 ; 2.751 ;; -1.346 ; T80se:z80_inst|T80:u0|DO[0] ; lcdvram[18][0] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 4.340 ; 2.514 ;; -1.283 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[2][2] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.370 ; 1.607 ;; -1.211 ; T80se:z80_inst|T80:u0|DO[1] ; lcdvram[10][1] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.377 ; 1.686 ;; -1.179 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[18][7] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 4.360 ; 2.701 ;; -1.153 ; T80se:z80_inst|T80:u0|DO[4] ; lcdvram[18][4] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 4.384 ; 2.751 ;; -1.151 ; T80se:z80_inst|T80:u0|DO[5] ; lcdvram[2][5] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.397 ; 1.766 ;; -1.148 ; T80se:z80_inst|T80:u0|DO[5] ; lcdvram[18][5] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 4.353 ; 2.725 ;; -1.133 ; T80se:z80_inst|T80:u0|DO[6] ; lcdvram[2][6] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.397 ; 1.784 ;; -1.054 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[26][2] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.401 ; 1.867 ;; -1.035 ; T80se:z80_inst|T80:u0|DO[0] ; lcdvram[26][0] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.400 ; 1.885 ;; -1.026 ; T80se:z80_inst|T80:u0|DO[4] ; lcdvram[24][4] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.432 ; 1.926 ;; -1.016 ; T80se:z80_inst|T80:u0|DO[4] ; lcdvram[2][4] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.054 ; 1.558 ;; -1.014 ; T80se:z80_inst|T80:u0|DO[4] ; lcdvram[26][4] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.248 ; 1.754 ;; -1.013 ; T80se:z80_inst|T80:u0|DO[4] ; lcdvram[10][4] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.608 ; 2.115 ;; -1.002 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[26][7] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.546 ; 2.064 ;; -0.975 ; T80se:z80_inst|T80:u0|DO[6] ; lcdvram[10][6] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.369 ; 1.914 ;; -0.971 ; T80se:z80_inst|T80:u0|DO[5] ; lcdvram[26][5] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.236 ; 1.785 ;; -0.969 ; T80se:z80_inst|T80:u0|DO[0] ; lcdvram[24][0] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.588 ; 2.139 ;; -0.965 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[26][3] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.305 ; 1.860 ;; -0.953 ; T80se:z80_inst|T80:u0|DO[1] ; lcdvram[2][1] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.120 ; 1.687 ;; -0.939 ; T80se:z80_inst|T80:u0|DO[0] ; lcdvram[2][0] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.053 ; 1.634 ;; -0.932 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[10][2] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.298 ; 1.886 ;; -0.927 ; T80se:z80_inst|T80:u0|DO[1] ; lcdvram[26][1] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.299 ; 1.892 ;; -0.909 ; T80se:z80_inst|T80:u0|DO[1] ; lcdvram[16][1] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.825 ; 2.436 ;; -0.907 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[2][7] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.540 ; 2.153 ;; -0.897 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[10][7] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.443 ; 2.066 ;; -0.879 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[8][3] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 2.462 ; 1.103 ;; -0.868 ; T80se:z80_inst|T80:u0|DO[5] ; lcdvram[10][5] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.134 ; 1.786 ;; -0.835 ; T80se:z80_inst|T80:u0|DO[0] ; lcdvram[10][0] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.443 ; 2.128 ;; -0.812 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[16][2] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.776 ; 2.484 ;; -0.795 ; T80se:z80_inst|T80:u0|DO[4] ; lcdvram[0][4] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.209 ; 1.934 ;; -0.794 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[10][3] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.135 ; 1.861 ;; -0.759 ; T80se:z80_inst|T80:u0|DO[4] ; lcdvram[16][4] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.637 ; 2.398 ;; -0.739 ; T80se:z80_inst|T80:u0|DO[6] ; lcdvram[26][6] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.101 ; 1.882 ;; -0.712 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[24][3] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.432 ; 2.240 ;; -0.677 ; T80se:z80_inst|T80:u0|DO[1] ; lcdvram[24][1] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.592 ; 2.435 ;; -0.668 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[24][7] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.457 ; 2.309 ;; -0.649 ; T80se:z80_inst|T80:u0|DO[6] ; lcdvram[16][6] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.616 ; 2.487 ;; -0.638 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[24][2] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.603 ; 2.485 ;; -0.611 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[2][3] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.171 ; 2.080 ;; -0.610 ; T80se:z80_inst|T80:u0|DO[1] ; lcdvram[8][1] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 2.462 ; 1.372 ;; -0.605 ; T80se:z80_inst|T80:u0|DO[0] ; lcdvram[0][0] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 2.679 ; 1.594 ;; -0.563 ; T80se:z80_inst|T80:u0|DO[1] ; lcdvram[4][1] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 4.259 ; 3.216 ;; -0.518 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[0][7] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.206 ; 2.208 ;; -0.511 ; T80se:z80_inst|T80:u0|DO[5] ; lcdvram[8][5] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 2.754 ; 1.763 ;; -0.501 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[16][7] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.780 ; 2.799 ;; -0.494 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[8][2] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 2.751 ; 1.777 ;; -0.479 ; T80se:z80_inst|T80:u0|DO[0] ; lcdvram[16][0] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.635 ; 2.676 ;; -0.471 ; T80se:z80_inst|T80:u0|DO[5] ; lcdvram[4][5] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 4.259 ; 3.308 ;; -0.459 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[20][2] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.870 ; 2.931 ;; -0.455 ; T80se:z80_inst|T80:u0|DO[1] ; lcdvram[20][1] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.884 ; 2.949 ;; -0.453 ; T80se:z80_inst|T80:u0|DO[4] ; lcdvram[8][4] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.048 ; 2.115 ;; -0.449 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[4][3] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 4.255 ; 3.326 ;; -0.448 ; T80se:z80_inst|T80:u0|DO[6] ; lcdvram[8][6] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 2.749 ; 1.821 ;; -0.446 ; T80se:z80_inst|T80:u0|DO[6] ; lcdvram[24][6] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.413 ; 2.487 ;; -0.443 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[20][7] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.920 ; 2.997 ;; -0.431 ; T80se:z80_inst|T80:u0|DO[6] ; lcdvram[0][6] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 2.583 ; 1.672 ;; -0.405 ; T80se:z80_inst|T80:u0|DO[5] ; lcdvram[16][5] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.610 ; 2.725 ;; -0.402 ; T80se:z80_inst|T80:u0|DO[4] ; lcdvram[28][4] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 4.069 ; 3.187 ;; -0.398 ; T80se:z80_inst|T80:u0|DO[6] ; lcdvram[20][6] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.887 ; 3.009 ;; -0.386 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[0][2] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 2.583 ; 1.717 ;; -0.381 ; T80se:z80_inst|T80:u0|DO[6] ; lcdvram[28][6] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.868 ; 3.007 ;; -0.372 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[8][7] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.006 ; 2.154 ;; -0.367 ; T80se:z80_inst|T80:u0|DO[0] ; lcdvram[4][0] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 4.092 ; 3.245 ;; -0.367 ; T80se:z80_inst|T80:u0|DO[0] ; lcdvram[28][0] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.889 ; 3.042 ;; -0.363 ; T80se:z80_inst|T80:u0|DO[5] ; lcdvram[0][5] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 2.162 ; 1.319 ;; -0.339 ; T80se:z80_inst|T80:u0|DO[5] ; lcdvram[24][5] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.459 ; 2.640 ;; -0.335 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[20][3] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.905 ; 3.090 ;; -0.332 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[28][2] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.866 ; 3.054 ;; -0.327 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[16][3] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.635 ; 2.828 ;; -0.326 ; T80se:z80_inst|T80:u0|DO[4] ; lcdvram[4][4] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 4.097 ; 3.291 ;; -0.320 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[28][3] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.887 ; 3.087 ;; -0.314 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[28][7] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 4.053 ; 3.259 ;; -0.308 ; T80se:z80_inst|T80:u0|DO[1] ; lcdvram[0][1] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 2.162 ; 1.374 ;; -0.285 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[4][7] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 4.071 ; 3.306 ;; -0.282 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[0][3] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 2.163 ; 1.401 ;; -0.267 ; T80se:z80_inst|T80:u0|DO[6] ; lcdvram[5][6] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.262 ; 2.515 ;; -0.252 ; T80se:z80_inst|T80:u0|DO[1] ; lcdvram[28][1] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.869 ; 3.137 ;; -0.251 ; T80se:z80_inst|T80:u0|DO[0] ; lcdvram[5][0] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.290 ; 2.559 ;; -0.224 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[4][2] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 4.070 ; 3.366 ;; -0.224 ; T80se:z80_inst|T80:u0|DO[4] ; lcdvram[19][4] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 2.919 ; 2.215 ;; -0.209 ; T80se:z80_inst|T80:u0|DO[0] ; lcdvram[19][0] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.117 ; 2.428 ;; -0.207 ; T80se:z80_inst|T80:u0|DO[6] ; lcdvram[4][6] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 4.067 ; 3.380 ;; -0.207 ; T80se:z80_inst|T80:u0|DO[0] ; lcdvram[20][0] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.921 ; 3.234 ;; -0.200 ; T80se:z80_inst|T80:u0|DO[5] ; lcdvram[28][5] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.876 ; 3.196 ;; -0.198 ; T80se:z80_inst|T80:u0|DO[0] ; lcdvram[6][0] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.706 ; 3.028 ;; -0.189 ; T80se:z80_inst|T80:u0|DO[4] ; lcdvram[6][4] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.718 ; 3.049 ;; -0.179 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[5][7] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.269 ; 2.610 ;; -0.154 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[19][3] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.120 ; 2.486 ;; -0.142 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[6][7] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.692 ; 3.070 ;; -0.138 ; T80se:z80_inst|T80:u0|DO[5] ; lcdvram[20][5] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.870 ; 3.252 ;; -0.138 ; T80se:z80_inst|T80:u0|DO[1] ; lcdvram[5][1] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.294 ; 2.676 ;; -0.134 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[6][3] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.700 ; 3.086 ;; -0.120 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[19][2] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.119 ; 2.519 ;; -0.113 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[5][2] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 3.263 ; 2.670 ;; -0.111 ; T80se:z80_inst|T80:u0|DO[4] ; lcdvram[30][4] ; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; -0.500 ; 2.819 ; 2.228 ;+--------+-----------------------------+----------------+---------------------------------+-----------------------+--------------+------------+------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Hold: 'ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered' ;+--------+--------------------------------------------------+----------------------------------------------------+-------------------------------------------------------------+-------------------------------------------------------------+--------------+------------+------------+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;+--------+--------------------------------------------------+----------------------------------------------------+-------------------------------------------------------------+-------------------------------------------------------------+--------------+------------+------------+; -0.418 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 3.746 ; 3.756 ;; -0.021 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; -0.500 ; 3.746 ; 3.653 ;; 0.403 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.080 ; 0.669 ;; 0.403 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.080 ; 0.669 ;; 0.408 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.080 ; 0.674 ;; 0.431 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[8] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[7] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.080 ; 0.697 ;; 0.450 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[7] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[6] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.080 ; 0.716 ;; 0.452 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.080 ; 0.718 ;; 0.453 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.080 ; 0.719 ;; 0.454 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[5] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[4] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.080 ; 0.720 ;; 0.454 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[4] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.080 ; 0.720 ;; 0.575 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[6] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[5] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.080 ; 0.841 ;; 0.575 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.080 ; 0.841 ;; 0.930 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.080 ; 1.196 ;; 0.945 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.080 ; 1.211 ;; 1.034 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.083 ; 1.303 ;; 1.035 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.083 ; 1.304 ;; 1.038 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.083 ; 1.307 ;; 1.053 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.080 ; 1.319 ;; 1.057 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.080 ; 1.323 ;; 1.067 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[4] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[4] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.083 ; 1.336 ;; 1.073 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[7] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[7] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 1.340 ;; 1.085 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.080 ; 1.351 ;; 1.095 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[6] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[6] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 1.362 ;; 1.115 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.080 ; 1.381 ;; 1.177 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.080 ; 1.443 ;; 1.236 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.080 ; 1.502 ;; 1.237 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.080 ; 1.503 ;; 1.243 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.080 ; 1.509 ;; 1.244 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.080 ; 1.510 ;; 1.266 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.080 ; 1.532 ;; 1.289 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[5] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[5] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.083 ; 1.558 ;; 1.345 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.080 ; 1.611 ;; 1.352 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.080 ; 1.618 ;; 1.353 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.080 ; 1.619 ;; 1.442 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.080 ; 1.708 ;; 1.442 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.080 ; 1.708 ;; 1.442 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.080 ; 1.708 ;; 1.442 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.080 ; 1.708 ;; 1.454 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.083 ; 1.723 ;; 1.523 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.080 ; 1.789 ;; 1.530 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.080 ; 1.796 ;; 1.533 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.080 ; 1.799 ;; 1.885 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[8] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.152 ;; 1.885 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[7] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.152 ;; 1.885 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[6] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.152 ;; 1.885 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[5] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.152 ;; 1.885 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[4] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.152 ;; 1.885 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.152 ;; 1.885 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.152 ;; 1.885 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.152 ;; 1.885 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.152 ;; 1.902 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[8] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.169 ;; 1.902 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[7] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.169 ;; 1.902 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[6] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.169 ;; 1.902 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[5] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.169 ;; 1.902 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[4] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.169 ;; 1.902 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.169 ;; 1.902 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.169 ;; 1.902 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.169 ;; 1.902 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.169 ;; 1.932 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.080 ; 2.198 ;; 1.994 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[8] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.261 ;; 1.994 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[7] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.261 ;; 1.994 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[6] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.261 ;; 1.994 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[5] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.261 ;; 1.994 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[4] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.261 ;; 1.994 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.261 ;; 1.994 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.261 ;; 1.994 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.261 ;; 1.994 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.261 ;; 2.061 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.080 ; 2.327 ;; 2.076 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.084 ; 2.346 ;; 2.076 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.084 ; 2.346 ;; 2.076 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[4] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.084 ; 2.346 ;; 2.076 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.084 ; 2.346 ;; 2.076 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.084 ; 2.346 ;; 2.160 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.084 ; 2.430 ;; 2.160 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.084 ; 2.430 ;; 2.160 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[4] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.084 ; 2.430 ;; 2.160 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.084 ; 2.430 ;; 2.160 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.084 ; 2.430 ;; 2.165 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.080 ; 2.431 ;; 2.172 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[8] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.439 ;; 2.172 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[7] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.439 ;; 2.172 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[6] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.439 ;; 2.172 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[5] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.439 ;; 2.172 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[4] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.439 ;; 2.172 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.439 ;; 2.172 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.439 ;; 2.172 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.439 ;; 2.172 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.439 ;; 2.182 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[8] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.449 ;; 2.182 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[7] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.449 ;; 2.182 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[6] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.449 ;; 2.182 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[5] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.449 ;; 2.182 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[4] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.449 ;; 2.182 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.449 ;; 2.182 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.449 ;; 2.182 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 0.000 ; 0.081 ; 2.449 ;+--------+--------------------------------------------------+----------------------------------------------------+-------------------------------------------------------------+-------------------------------------------------------------+--------------+------------+------------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Hold: 'clk_div:clkdiv_inst|clock_1Mhz_int' ;+--------+--------------------------------------+--------------------------------------+--------------------------------------+------------------------------------+--------------+------------+------------+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;+--------+--------------------------------------+--------------------------------------+--------------------------------------+------------------------------------+--------------+------------+------------+; -0.319 ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_1Mhz_int ; 0.000 ; 2.270 ; 2.369 ;; 0.203 ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_1Mhz_int ; -0.500 ; 2.270 ; 2.391 ;; 0.440 ; clk_div:clkdiv_inst|count_100Khz[2] ; clk_div:clkdiv_inst|count_100Khz[2] ; clk_div:clkdiv_inst|clock_1Mhz_int ; clk_div:clkdiv_inst|clock_1Mhz_int ; 0.000 ; 0.043 ; 0.669 ;; 0.440 ; clk_div:clkdiv_inst|count_100Khz[1] ; clk_div:clkdiv_inst|count_100Khz[1] ; clk_div:clkdiv_inst|clock_1Mhz_int ; clk_div:clkdiv_inst|clock_1Mhz_int ; 0.000 ; 0.043 ; 0.669 ;; 0.445 ; clk_div:clkdiv_inst|count_100Khz[0] ; clk_div:clkdiv_inst|count_100Khz[0] ; clk_div:clkdiv_inst|clock_1Mhz_int ; clk_div:clkdiv_inst|clock_1Mhz_int ; 0.000 ; 0.043 ; 0.674 ;; 0.469 ; clk_div:clkdiv_inst|count_100Khz[1] ; clk_div:clkdiv_inst|count_100Khz[2] ; clk_div:clkdiv_inst|clock_1Mhz_int ; clk_div:clkdiv_inst|clock_1Mhz_int ; 0.000 ; 0.046 ; 0.701 ;; 0.487 ; clk_div:clkdiv_inst|count_100Khz[0] ; clk_div:clkdiv_inst|count_100Khz[1] ; clk_div:clkdiv_inst|clock_1Mhz_int ; clk_div:clkdiv_inst|clock_1Mhz_int ; 0.000 ; 0.046 ; 0.719 ;; 0.645 ; clk_div:clkdiv_inst|count_100Khz[2] ; clk_div:clkdiv_inst|count_100Khz[0] ; clk_div:clkdiv_inst|clock_1Mhz_int ; clk_div:clkdiv_inst|clock_1Mhz_int ; 0.000 ; 0.046 ; 0.877 ;; 0.691 ; clk_div:clkdiv_inst|count_100Khz[1] ; clk_div:clkdiv_inst|count_100Khz[0] ; clk_div:clkdiv_inst|clock_1Mhz_int ; clk_div:clkdiv_inst|clock_1Mhz_int ; 0.000 ; 0.046 ; 0.923 ;; 0.704 ; clk_div:clkdiv_inst|count_100Khz[0] ; clk_div:clkdiv_inst|count_100Khz[2] ; clk_div:clkdiv_inst|clock_1Mhz_int ; clk_div:clkdiv_inst|clock_1Mhz_int ; 0.000 ; 0.046 ; 0.936 ;; 0.810 ; clk_div:clkdiv_inst|count_100Khz[1] ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_1Mhz_int ; clk_div:clkdiv_inst|clock_1Mhz_int ; 0.000 ; 0.046 ; 1.042 ;; 0.941 ; clk_div:clkdiv_inst|count_100Khz[2] ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_1Mhz_int ; clk_div:clkdiv_inst|clock_1Mhz_int ; 0.000 ; 0.046 ; 1.173 ;; 1.251 ; clk_div:clkdiv_inst|count_100Khz[0] ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_1Mhz_int ; clk_div:clkdiv_inst|clock_1Mhz_int ; 0.000 ; 0.046 ; 1.483 ;+--------+--------------------------------------+--------------------------------------+--------------------------------------+------------------------------------+--------------+------------+------------++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Hold: 'CLOCK_50' ;+--------+-------------------------------------------------------------+-------------------------------------------------------------+-------------------------------------------------------------+-------------+--------------+------------+------------+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;+--------+-------------------------------------------------------------+-------------------------------------------------------------+-------------------------------------------------------------+-------------+--------------+------------+------------+; -0.260 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50 ; 0.000 ; 3.044 ; 3.232 ;; -0.232 ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_1KHz ; clk_div:clkdiv_inst|clock_1Khz_int ; CLOCK_50 ; 0.000 ; 3.179 ; 3.385 ;; -0.161 ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; CLOCK_50 ; 0.000 ; 2.997 ; 3.274 ;; -0.050 ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25Mhz_int ; CLOCK_50 ; 0.000 ; 2.997 ; 3.385 ;; 0.219 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50 ; -0.500 ; 3.044 ; 3.211 ;; 0.278 ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_1KHz ; clk_div:clkdiv_inst|clock_1Khz_int ; CLOCK_50 ; -0.500 ; 3.179 ; 3.395 ;; 0.320 ; clk_div:clkdiv_inst|clock_100hz_int ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_1Khz_int ; CLOCK_50 ; 0.000 ; 1.766 ; 2.292 ;; 0.378 ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; CLOCK_50 ; -0.500 ; 2.997 ; 3.313 ;; 0.402 ; LCD:lcd_inst|data_bus_value[0] ; LCD:lcd_inst|data_bus_value[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.669 ;; 0.402 ; LCD:lcd_inst|data_bus_value[6] ; LCD:lcd_inst|data_bus_value[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.669 ;; 0.402 ; clk_div:clkdiv_inst|count_357Mhz[3] ; clk_div:clkdiv_inst|count_357Mhz[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.669 ;; 0.402 ; clk_div:clkdiv_inst|count_357Mhz[2] ; clk_div:clkdiv_inst|count_357Mhz[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.669 ;; 0.402 ; clk_div:clkdiv_inst|count_357Mhz[1] ; clk_div:clkdiv_inst|count_357Mhz[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.669 ;; 0.402 ; clk_div:clkdiv_inst|clock_357Mhz_int ; clk_div:clkdiv_inst|clock_357Mhz_int ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.669 ;; 0.403 ; LCD:lcd_inst|next_command.reset2 ; LCD:lcd_inst|next_command.reset2 ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.669 ;; 0.403 ; LCD:lcd_inst|next_command.reset3 ; LCD:lcd_inst|next_command.reset3 ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.669 ;; 0.403 ; LCD:lcd_inst|next_command.func_set ; LCD:lcd_inst|next_command.func_set ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.669 ;; 0.403 ; LCD:lcd_inst|next_command.display_off ; LCD:lcd_inst|next_command.display_off ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.669 ;; 0.403 ; LCD:lcd_inst|next_command.display_clear ; LCD:lcd_inst|next_command.display_clear ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.669 ;; 0.403 ; LCD:lcd_inst|next_command.display_on ; LCD:lcd_inst|next_command.display_on ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.669 ;; 0.403 ; LCD:lcd_inst|next_command.mode_set ; LCD:lcd_inst|next_command.mode_set ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.669 ;; 0.403 ; LCD:lcd_inst|next_command.line2 ; LCD:lcd_inst|next_command.line2 ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.669 ;; 0.403 ; LCD:lcd_inst|data_bus_value[7] ; LCD:lcd_inst|data_bus_value[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.669 ;; 0.403 ; LCD:lcd_inst|LCD_RS ; LCD:lcd_inst|LCD_RS ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.669 ;; 0.403 ; LCD:lcd_inst|LCD_EN ; LCD:lcd_inst|LCD_EN ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.669 ;; 0.403 ; LCD:lcd_inst|LCD_ON ; LCD:lcd_inst|LCD_ON ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.669 ;; 0.403 ; clk_div:clkdiv_inst|count_10Mhz[1] ; clk_div:clkdiv_inst|count_10Mhz[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.669 ;; 0.403 ; clk_div:clkdiv_inst|count_10Mhz[2] ; clk_div:clkdiv_inst|count_10Mhz[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.669 ;; 0.403 ; clk_div:clkdiv_inst|clock_10Mhz_int ; clk_div:clkdiv_inst|clock_10Mhz_int ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.669 ;; 0.407 ; clk_div:clkdiv_inst|count_357Mhz[0] ; clk_div:clkdiv_inst|count_357Mhz[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.674 ;; 0.408 ; LCD:lcd_inst|state.drop_LCD_EN ; LCD:lcd_inst|state.drop_LCD_EN ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.674 ;; 0.408 ; clk_div:clkdiv_inst|count_10Mhz[0] ; clk_div:clkdiv_inst|count_10Mhz[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.674 ;; 0.422 ; LCD:lcd_inst|next_command.reset2 ; LCD:lcd_inst|state.reset2 ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.688 ;; 0.428 ; LCD:lcd_inst|clk_count_400hz[19] ; LCD:lcd_inst|clk_count_400hz[19] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.694 ;; 0.430 ; LCD:lcd_inst|next_command.display_clear ; LCD:lcd_inst|state.display_clear ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.696 ;; 0.430 ; LCD:lcd_inst|next_command.mode_set ; LCD:lcd_inst|state.mode_set ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.696 ;; 0.430 ; \random:rand_temp[1] ; \random:rand_temp[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.697 ;; 0.430 ; clk_div:clkdiv_inst|count_10Mhz[2] ; clk_div:clkdiv_inst|count_10Mhz[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.696 ;; 0.431 ; LCD:lcd_inst|next_command.func_set ; LCD:lcd_inst|state.func_set ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.697 ;; 0.431 ; LCD:lcd_inst|next_command.display_off ; LCD:lcd_inst|state.display_off ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.697 ;; 0.432 ; clk_div:clkdiv_inst|count_10Mhz[2] ; clk_div:clkdiv_inst|clock_10Mhz_int ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.698 ;; 0.435 ; clk_div:clkdiv_inst|clock_357Mhz_int ; clk_div:clkdiv_inst|clock_357Mhz ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.245 ; 0.866 ;; 0.435 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|filter[6] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|filter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.701 ;; 0.436 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|filter[4] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|filter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.702 ;; 0.436 ; clk_div:clkdiv_inst|count_357Mhz[0] ; clk_div:clkdiv_inst|count_357Mhz[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.703 ;; 0.437 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|filter[3] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|filter[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.703 ;; 0.440 ; clk_div:clkdiv_inst|count_357Mhz[1] ; clk_div:clkdiv_inst|clock_357Mhz_int ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.707 ;; 0.442 ; clk_div:clkdiv_inst|count_357Mhz[1] ; clk_div:clkdiv_inst|count_357Mhz[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.709 ;; 0.442 ; clk_div:clkdiv_inst|count_357Mhz[1] ; clk_div:clkdiv_inst|count_357Mhz[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.709 ;; 0.443 ; clk_div:clkdiv_inst|count_357Mhz[3] ; clk_div:clkdiv_inst|count_357Mhz[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.710 ;; 0.444 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|filter[2] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|filter[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.710 ;; 0.450 ; \random:rand_temp[7] ; \random:rand_temp[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.717 ;; 0.451 ; LCD:lcd_inst|state.reset3 ; LCD:lcd_inst|next_command.func_set ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.717 ;; 0.451 ; \random:rand_temp[2] ; \random:rand_temp[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.718 ;; 0.452 ; \random:rand_temp[3] ; \random:rand_temp[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.719 ;; 0.454 ; clk_div:clkdiv_inst|count_10Mhz[1] ; clk_div:clkdiv_inst|count_10Mhz[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.720 ;; 0.459 ; LCD:lcd_inst|state.display_clear ; LCD:lcd_inst|next_command.display_on ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.725 ;; 0.491 ; LCD:lcd_inst|state.hold ; LCD:lcd_inst|state.drop_LCD_EN ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.757 ;; 0.493 ; LCD:lcd_inst|state.hold ; LCD:lcd_inst|state.return_home ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.759 ;; 0.494 ; LCD:lcd_inst|state.hold ; LCD:lcd_inst|state.print_string ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.760 ;; 0.497 ; LCD:lcd_inst|state.hold ; LCD:lcd_inst|state.line2 ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.763 ;; 0.501 ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25Mhz_int ; CLOCK_50 ; -0.500 ; 2.997 ; 3.436 ;; 0.552 ; \random:rand_temp[13] ; \random:rand_temp[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.819 ;; 0.554 ; LCD:lcd_inst|next_command.line2 ; LCD:lcd_inst|state.line2 ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.820 ;; 0.555 ; LCD:lcd_inst|next_command.reset3 ; LCD:lcd_inst|state.reset3 ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.821 ;; 0.555 ; LCD:lcd_inst|next_command.display_on ; LCD:lcd_inst|state.display_on ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.821 ;; 0.560 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|filter[7] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|filter[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.826 ;; 0.563 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|filter[5] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|filter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.829 ;; 0.576 ; \random:rand_temp[4] ; \random:rand_temp[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.843 ;; 0.600 ; LCD:lcd_inst|state.print_string ; LCD:lcd_inst|next_command.return_home ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.866 ;; 0.600 ; \random:rand_temp[11] ; \random:rand_temp[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.867 ;; 0.601 ; LCD:lcd_inst|state.print_string ; LCD:lcd_inst|next_command.print_string ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.867 ;; 0.609 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|filter[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|filter[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.875 ;; 0.612 ; ps2_read ; ps2_ascii_reg1[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.878 ;; 0.612 ; ps2_read ; ps2_ascii_reg1[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.878 ;; 0.612 ; ps2_read ; ps2_ascii_reg1[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.878 ;; 0.612 ; ps2_read ; ps2_ascii_reg1[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.878 ;; 0.621 ; \random:rand_temp[9] ; \random:rand_temp[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.888 ;; 0.621 ; \random:rand_temp[0] ; \random:rand_temp[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.888 ;; 0.639 ; ps2_read ; ps2_ascii_reg1[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.905 ;; 0.640 ; LCD:lcd_inst|state.print_string ; LCD:lcd_inst|LCD_RS ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.079 ; 0.905 ;; 0.641 ; LCD:lcd_inst|clk_count_400hz[5] ; LCD:lcd_inst|clk_count_400hz[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.907 ;; 0.641 ; LCD:lcd_inst|clk_count_400hz[13] ; LCD:lcd_inst|clk_count_400hz[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.907 ;; 0.642 ; LCD:lcd_inst|clk_count_400hz[15] ; LCD:lcd_inst|clk_count_400hz[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.908 ;; 0.644 ; LCD:lcd_inst|clk_count_400hz[3] ; LCD:lcd_inst|clk_count_400hz[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.910 ;; 0.645 ; LCD:lcd_inst|clk_count_400hz[10] ; LCD:lcd_inst|clk_count_400hz[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.911 ;; 0.645 ; LCD:lcd_inst|clk_count_400hz[16] ; LCD:lcd_inst|clk_count_400hz[16] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.911 ;; 0.645 ; LCD:lcd_inst|state.reset2 ; LCD:lcd_inst|next_command.reset3 ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.911 ;; 0.646 ; LCD:lcd_inst|clk_count_400hz[17] ; LCD:lcd_inst|clk_count_400hz[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.912 ;; 0.646 ; LCD:lcd_inst|clk_count_400hz[12] ; LCD:lcd_inst|clk_count_400hz[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.912 ;; 0.646 ; LCD:lcd_inst|state.func_set ; LCD:lcd_inst|next_command.display_off ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.912 ;; 0.647 ; LCD:lcd_inst|clk_count_400hz[4] ; LCD:lcd_inst|clk_count_400hz[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.913 ;; 0.647 ; LCD:lcd_inst|clk_count_400hz[14] ; LCD:lcd_inst|clk_count_400hz[14] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.913 ;; 0.648 ; LCD:lcd_inst|clk_count_400hz[2] ; LCD:lcd_inst|clk_count_400hz[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.914 ;; 0.648 ; LCD:lcd_inst|next_command.print_string ; LCD:lcd_inst|state.print_string ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.914 ;; 0.649 ; LCD:lcd_inst|clk_count_400hz[18] ; LCD:lcd_inst|clk_count_400hz[18] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.915 ;; 0.649 ; LCD:lcd_inst|next_command.return_home ; LCD:lcd_inst|state.return_home ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.915 ;; 0.652 ; clk_div:clkdiv_inst|count_357Mhz[0] ; clk_div:clkdiv_inst|count_357Mhz[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.919 ;; 0.652 ; clk_div:clkdiv_inst|count_357Mhz[0] ; clk_div:clkdiv_inst|count_357Mhz[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.919 ;; 0.654 ; LCD:lcd_inst|state.display_off ; LCD:lcd_inst|next_command.display_clear ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.920 ;+--------+-------------------------------------------------------------+-------------------------------------------------------------+-------------------------------------------------------------+-------------+--------------+------------+------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Hold: 'clk_div:clkdiv_inst|clock_10Khz_int' ;+--------+------------------------------------+------------------------------------+-------------------------------------+-------------------------------------+--------------+------------+------------+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;+--------+------------------------------------+------------------------------------+-------------------------------------+-------------------------------------+--------------+------------+------------+; -0.127 ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; 0.000 ; 1.431 ; 1.722 ;; 0.391 ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; -0.500 ; 1.431 ; 1.740 ;; 0.440 ; clk_div:clkdiv_inst|count_1Khz[2] ; clk_div:clkdiv_inst|count_1Khz[2] ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; 0.000 ; 0.043 ; 0.669 ;; 0.440 ; clk_div:clkdiv_inst|count_1Khz[1] ; clk_div:clkdiv_inst|count_1Khz[1] ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; 0.000 ; 0.043 ; 0.669 ;; 0.445 ; clk_div:clkdiv_inst|count_1Khz[0] ; clk_div:clkdiv_inst|count_1Khz[0] ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; 0.000 ; 0.043 ; 0.674 ;; 0.469 ; clk_div:clkdiv_inst|count_1Khz[1] ; clk_div:clkdiv_inst|count_1Khz[2] ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; 0.000 ; 0.045 ; 0.700 ;; 0.473 ; clk_div:clkdiv_inst|count_1Khz[0] ; clk_div:clkdiv_inst|count_1Khz[1] ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; 0.000 ; 0.045 ; 0.704 ;; 0.690 ; clk_div:clkdiv_inst|count_1Khz[0] ; clk_div:clkdiv_inst|count_1Khz[2] ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; 0.000 ; 0.045 ; 0.921 ;; 0.691 ; clk_div:clkdiv_inst|count_1Khz[1] ; clk_div:clkdiv_inst|count_1Khz[0] ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; 0.000 ; 0.045 ; 0.922 ;; 0.710 ; clk_div:clkdiv_inst|count_1Khz[2] ; clk_div:clkdiv_inst|count_1Khz[0] ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; 0.000 ; 0.045 ; 0.941 ;; 0.810 ; clk_div:clkdiv_inst|count_1Khz[1] ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; 0.000 ; 0.045 ; 1.041 ;; 0.924 ; clk_div:clkdiv_inst|count_1Khz[2] ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; 0.000 ; 0.045 ; 1.155 ;; 1.078 ; clk_div:clkdiv_inst|count_1Khz[0] ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; 0.000 ; 0.045 ; 1.309 ;+--------+------------------------------------+------------------------------------+-------------------------------------+-------------------------------------+--------------+------------+------------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Hold: 'clk_div:clkdiv_inst|clock_25MHz' ;+-------+-----------------------------+--------------------------------------------------------------------------------------------------------------+---------------------------------+---------------------------------+--------------+------------+------------+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;+-------+-----------------------------+--------------------------------------------------------------------------------------------------------------+---------------------------------+---------------------------------+--------------+------------+------------+; 0.048 ; T80se:z80_inst|T80:u0|A[3] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a3~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.741 ; 2.031 ;; 0.067 ; T80se:z80_inst|T80:u0|A[7] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a9~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.068 ; 2.377 ;; 0.069 ; T80se:z80_inst|T80:u0|A[3] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a7~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.742 ; 2.053 ;; 0.086 ; T80se:z80_inst|T80:u0|A[8] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a8~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.052 ; 2.380 ;; 0.092 ; T80se:z80_inst|T80:u0|A[8] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a11~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.052 ; 2.386 ;; 0.106 ; T80se:z80_inst|T80:u0|A[8] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a13~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.050 ; 2.398 ;; 0.109 ; T80se:z80_inst|T80:u0|A[13] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a7~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.067 ; 2.418 ;; 0.110 ; T80se:z80_inst|T80:u0|A[13] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a3~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.066 ; 2.418 ;; 0.110 ; T80se:z80_inst|T80:u0|A[7] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a10~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.068 ; 2.420 ;; 0.113 ; T80se:z80_inst|T80:u0|A[8] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a12~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.048 ; 2.403 ;; 0.115 ; T80se:z80_inst|T80:u0|A[13] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a9~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.064 ; 2.421 ;; 0.115 ; T80se:z80_inst|T80:u0|A[7] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a7~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.071 ; 2.428 ;; 0.128 ; T80se:z80_inst|T80:u0|A[0] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a10~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.034 ; 2.404 ;; 0.130 ; T80se:z80_inst|T80:u0|A[0] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a2~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.021 ; 2.393 ;; 0.130 ; T80se:z80_inst|T80:u0|A[13] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a10~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.064 ; 2.436 ;; 0.134 ; T80se:z80_inst|T80:u0|A[13] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a1~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.058 ; 2.434 ;; 0.136 ; T80se:z80_inst|T80:u0|A[8] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a6~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.053 ; 2.431 ;; 0.139 ; T80se:z80_inst|T80:u0|A[8] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a2~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.055 ; 2.436 ;; 0.152 ; T80se:z80_inst|T80:u0|A[2] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a12~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.719 ; 2.113 ;; 0.153 ; T80se:z80_inst|T80:u0|A[1] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a13~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.721 ; 2.116 ;; 0.154 ; T80se:z80_inst|T80:u0|A[2] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a15~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.722 ; 2.118 ;; 0.156 ; T80se:z80_inst|T80:u0|A[2] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a11~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.723 ; 2.121 ;; 0.157 ; T80se:z80_inst|T80:u0|A[0] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a13~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.016 ; 2.415 ;; 0.165 ; T80se:z80_inst|T80:u0|A[2] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a13~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.721 ; 2.128 ;; 0.166 ; T80se:z80_inst|T80:u0|A[0] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a15~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.017 ; 2.425 ;; 0.170 ; T80se:z80_inst|T80:u0|A[0] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a11~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.018 ; 2.430 ;; 0.171 ; T80se:z80_inst|T80:u0|A[7] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a1~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.062 ; 2.475 ;; 0.172 ; T80se:z80_inst|T80:u0|A[1] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a11~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.723 ; 2.137 ;; 0.186 ; T80se:z80_inst|T80:u0|A[1] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a2~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.726 ; 2.154 ;; 0.187 ; T80se:z80_inst|T80:u0|A[7] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a13~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.050 ; 2.479 ;; 0.189 ; T80se:z80_inst|T80:u0|A[2] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a8~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.723 ; 2.154 ;; 0.192 ; T80se:z80_inst|T80:u0|A[2] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a2~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.726 ; 2.160 ;; 0.193 ; T80se:z80_inst|T80:u0|A[2] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a6~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.724 ; 2.159 ;; 0.195 ; T80se:z80_inst|T80:u0|A[13] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a15~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.047 ; 2.484 ;; 0.195 ; T80se:z80_inst|T80:u0|A[13] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a5~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.064 ; 2.501 ;; 0.196 ; T80se:z80_inst|T80:u0|A[0] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a12~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.014 ; 2.452 ;; 0.201 ; T80se:z80_inst|T80:u0|A[1] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a5~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.739 ; 2.182 ;; 0.202 ; T80se:z80_inst|T80:u0|A[4] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a9~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.739 ; 2.183 ;; 0.204 ; T80se:z80_inst|T80:u0|A[1] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a3~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.741 ; 2.187 ;; 0.207 ; T80se:z80_inst|T80:u0|A[3] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a1~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.733 ; 2.182 ;; 0.208 ; T80se:z80_inst|T80:u0|A[1] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a7~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.742 ; 2.192 ;; 0.209 ; T80se:z80_inst|T80:u0|A[13] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a6~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.049 ; 2.500 ;; 0.209 ; T80se:z80_inst|T80:u0|A[13] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a11~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.048 ; 2.499 ;; 0.210 ; T80se:z80_inst|T80:u0|A[0] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a3~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.036 ; 2.488 ;; 0.214 ; T80se:z80_inst|T80:u0|A[0] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a1~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.028 ; 2.484 ;; 0.214 ; T80se:z80_inst|T80:u0|A[13] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a2~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.051 ; 2.507 ;; 0.218 ; T80se:z80_inst|T80:u0|A[13] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a8~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.048 ; 2.508 ;; 0.223 ; T80se:z80_inst|T80:u0|A[0] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a0~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.031 ; 2.496 ;; 0.225 ; T80se:z80_inst|T80:u0|A[13] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a13~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.046 ; 2.513 ;; 0.225 ; T80se:z80_inst|T80:u0|A[0] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a4~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.033 ; 2.500 ;; 0.226 ; T80se:z80_inst|T80:u0|A[2] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a1~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.733 ; 2.201 ;; 0.233 ; T80se:z80_inst|T80:u0|A[1] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a15~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.722 ; 2.197 ;; 0.234 ; T80se:z80_inst|T80:u0|A[0] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a9~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.034 ; 2.510 ;; 0.234 ; T80se:z80_inst|T80:u0|A[13] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a12~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.044 ; 2.520 ;; 0.235 ; T80se:z80_inst|T80:u0|A[0] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a5~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.034 ; 2.511 ;; 0.238 ; T80se:z80_inst|T80:u0|A[1] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a9~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.739 ; 2.219 ;; 0.239 ; T80se:z80_inst|T80:u0|A[3] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a10~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.739 ; 2.220 ;; 0.241 ; T80se:z80_inst|T80:u0|A[8] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a15~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.051 ; 2.534 ;; 0.242 ; T80se:z80_inst|T80:u0|A[7] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a0~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.065 ; 2.549 ;; 0.243 ; T80se:z80_inst|T80:u0|A[7] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a5~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.068 ; 2.553 ;; 0.243 ; T80se:z80_inst|T80:u0|A[7] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a2~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.055 ; 2.540 ;; 0.243 ; T80se:z80_inst|T80:u0|A[1] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a4~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.738 ; 2.223 ;; 0.244 ; T80se:z80_inst|T80:u0|A[4] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a10~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.739 ; 2.225 ;; 0.245 ; T80se:z80_inst|T80:u0|A[3] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a0~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.736 ; 2.223 ;; 0.249 ; T80se:z80_inst|T80:u0|A[7] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a14~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.042 ; 2.533 ;; 0.249 ; T80se:z80_inst|T80:u0|A[4] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a7~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.742 ; 2.233 ;; 0.249 ; T80se:z80_inst|T80:u0|A[4] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a3~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.741 ; 2.232 ;; 0.250 ; T80se:z80_inst|T80:u0|A[7] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a12~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.048 ; 2.540 ;; 0.251 ; T80se:z80_inst|T80:u0|A[1] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a6~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.724 ; 2.217 ;; 0.262 ; T80se:z80_inst|T80:u0|A[13] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a14~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.038 ; 2.542 ;; 0.262 ; T80se:z80_inst|T80:u0|A[1] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a8~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.723 ; 2.227 ;; 0.262 ; T80se:z80_inst|T80:u0|A[7] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a3~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.070 ; 2.574 ;; 0.263 ; T80se:z80_inst|T80:u0|A[2] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a0~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.736 ; 2.241 ;; 0.266 ; T80se:z80_inst|T80:u0|A[2] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a5~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.739 ; 2.247 ;; 0.267 ; T80se:z80_inst|T80:u0|A[2] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a4~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.738 ; 2.247 ;; 0.268 ; T80se:z80_inst|T80:u0|A[0] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a7~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.037 ; 2.547 ;; 0.270 ; T80se:z80_inst|T80:u0|A[3] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a12~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.719 ; 2.231 ;; 0.272 ; T80se:z80_inst|T80:u0|A[2] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a9~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.739 ; 2.253 ;; 0.274 ; T80se:z80_inst|T80:u0|A[7] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a6~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.053 ; 2.569 ;; 0.274 ; T80se:z80_inst|T80:u0|A[7] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a8~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.052 ; 2.568 ;; 0.274 ; T80se:z80_inst|T80:u0|A[7] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a15~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.051 ; 2.567 ;; 0.275 ; T80se:z80_inst|T80:u0|A[8] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a9~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.068 ; 2.585 ;; 0.275 ; T80se:z80_inst|T80:u0|A[3] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a5~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.739 ; 2.256 ;; 0.276 ; T80se:z80_inst|T80:u0|A[10] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a0~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.767 ; 2.285 ;; 0.278 ; T80se:z80_inst|T80:u0|A[1] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a10~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.739 ; 2.259 ;; 0.280 ; T80se:z80_inst|T80:u0|A[1] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a1~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.733 ; 2.255 ;; 0.280 ; T80se:z80_inst|T80:u0|A[7] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a4~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.067 ; 2.589 ;; 0.282 ; T80se:z80_inst|T80:u0|A[8] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a5~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.068 ; 2.592 ;; 0.285 ; T80se:z80_inst|T80:u0|A[7] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a11~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.052 ; 2.579 ;; 0.286 ; T80se:z80_inst|T80:u0|A[8] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a10~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.068 ; 2.596 ;; 0.286 ; T80se:z80_inst|T80:u0|A[4] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a12~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.719 ; 2.247 ;; 0.291 ; T80se:z80_inst|T80:u0|A[13] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a4~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.063 ; 2.596 ;; 0.309 ; T80se:z80_inst|T80:u0|A[8] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a14~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.042 ; 2.593 ;; 0.309 ; T80se:z80_inst|T80:u0|A[10] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a5~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.770 ; 2.321 ;; 0.310 ; T80se:z80_inst|T80:u0|A[1] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a0~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.736 ; 2.288 ;; 0.311 ; T80se:z80_inst|T80:u0|A[0] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a6~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.019 ; 2.572 ;; 0.312 ; T80se:z80_inst|T80:u0|A[10] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a4~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.769 ; 2.323 ;; 0.315 ; T80se:z80_inst|T80:u0|A[8] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a7~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 2.071 ; 2.628 ;; 0.317 ; T80se:z80_inst|T80:u0|A[3] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a9~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.739 ; 2.298 ;; 0.321 ; T80se:z80_inst|T80:u0|A[4] ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a5~porta_address_reg0 ; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 0.000 ; 1.739 ; 2.302 ;+-------+-----------------------------+--------------------------------------------------------------------------------------------------------------+---------------------------------+---------------------------------+--------------+------------+------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Hold: 'clk_div:clkdiv_inst|clock_100Khz_int' ;+-------+-------------------------------------+-------------------------------------+--------------------------------------+--------------------------------------+--------------+------------+------------+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;+-------+-------------------------------------+-------------------------------------+--------------------------------------+--------------------------------------+--------------+------------+------------+; 0.106 ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; 0.000 ; 0.919 ; 1.443 ;; 0.440 ; clk_div:clkdiv_inst|count_10Khz[2] ; clk_div:clkdiv_inst|count_10Khz[2] ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; 0.000 ; 0.043 ; 0.669 ;; 0.440 ; clk_div:clkdiv_inst|count_10Khz[1] ; clk_div:clkdiv_inst|count_10Khz[1] ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; 0.000 ; 0.043 ; 0.669 ;; 0.445 ; clk_div:clkdiv_inst|count_10Khz[0] ; clk_div:clkdiv_inst|count_10Khz[0] ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; 0.000 ; 0.043 ; 0.674 ;; 0.479 ; clk_div:clkdiv_inst|count_10Khz[1] ; clk_div:clkdiv_inst|count_10Khz[0] ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; 0.000 ; 0.047 ; 0.712 ;; 0.647 ; clk_div:clkdiv_inst|count_10Khz[0] ; clk_div:clkdiv_inst|count_10Khz[1] ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; 0.000 ; 0.047 ; 0.880 ;; 0.647 ; clk_div:clkdiv_inst|count_10Khz[0] ; clk_div:clkdiv_inst|count_10Khz[2] ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; 0.000 ; 0.047 ; 0.880 ;; 0.652 ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; -0.500 ; 0.919 ; 1.489 ;; 0.686 ; clk_div:clkdiv_inst|count_10Khz[1] ; clk_div:clkdiv_inst|count_10Khz[2] ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; 0.000 ; 0.047 ; 0.919 ;; 0.774 ; clk_div:clkdiv_inst|count_10Khz[2] ; clk_div:clkdiv_inst|count_10Khz[0] ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; 0.000 ; 0.047 ; 1.007 ;; 0.808 ; clk_div:clkdiv_inst|count_10Khz[1] ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; 0.000 ; 0.047 ; 1.041 ;; 0.923 ; clk_div:clkdiv_inst|count_10Khz[2] ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; 0.000 ; 0.047 ; 1.156 ;; 1.086 ; clk_div:clkdiv_inst|count_10Khz[0] ; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; 0.000 ; 0.047 ; 1.319 ;+-------+-------------------------------------+-------------------------------------+--------------------------------------+--------------------------------------+--------------+------------+------------++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Hold: 'clk_div:clkdiv_inst|clock_1Khz_int' ;+-------+-------------------------------------+-------------------------------------+------------------------------------+------------------------------------+--------------+------------+------------+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;+-------+-------------------------------------+-------------------------------------+------------------------------------+------------------------------------+--------------+------------+------------+; 0.440 ; clk_div:clkdiv_inst|count_100hz[2] ; clk_div:clkdiv_inst|count_100hz[2] ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; 0.000 ; 0.043 ; 0.669 ;; 0.440 ; clk_div:clkdiv_inst|count_100hz[1] ; clk_div:clkdiv_inst|count_100hz[1] ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; 0.000 ; 0.043 ; 0.669 ;; 0.440 ; clk_div:clkdiv_inst|clock_100hz_int ; clk_div:clkdiv_inst|clock_100hz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; 0.000 ; 0.043 ; 0.669 ;; 0.445 ; clk_div:clkdiv_inst|count_100hz[0] ; clk_div:clkdiv_inst|count_100hz[0] ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; 0.000 ; 0.043 ; 0.674 ;; 0.462 ; clk_div:clkdiv_inst|count_100hz[2] ; clk_div:clkdiv_inst|count_100hz[0] ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; 0.000 ; 0.047 ; 0.695 ;; 0.469 ; clk_div:clkdiv_inst|count_100hz[1] ; clk_div:clkdiv_inst|clock_100hz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; 0.000 ; 0.047 ; 0.702 ;; 0.469 ; clk_div:clkdiv_inst|count_100hz[1] ; clk_div:clkdiv_inst|count_100hz[2] ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; 0.000 ; 0.047 ; 0.702 ;; 0.483 ; clk_div:clkdiv_inst|count_100hz[0] ; clk_div:clkdiv_inst|count_100hz[1] ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; 0.000 ; 0.047 ; 0.716 ;; 0.689 ; clk_div:clkdiv_inst|count_100hz[1] ; clk_div:clkdiv_inst|count_100hz[0] ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; 0.000 ; 0.047 ; 0.922 ;; 0.703 ; clk_div:clkdiv_inst|count_100hz[0] ; clk_div:clkdiv_inst|count_100hz[2] ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; 0.000 ; 0.047 ; 0.936 ;; 0.752 ; clk_div:clkdiv_inst|count_100hz[2] ; clk_div:clkdiv_inst|clock_100hz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; 0.000 ; 0.047 ; 0.985 ;; 0.902 ; clk_div:clkdiv_inst|count_100hz[0] ; clk_div:clkdiv_inst|clock_100hz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; 0.000 ; 0.047 ; 1.135 ;+-------+-------------------------------------+-------------------------------------+------------------------------------+------------------------------------+--------------+------------+------------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Hold: 'clk_div:clkdiv_inst|clock_25Mhz_int' ;+-------+-----------------------------------+------------------------------------+-------------------------------------+-------------------------------------+--------------+------------+------------+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;+-------+-----------------------------------+------------------------------------+-------------------------------------+-------------------------------------+--------------+------------+------------+; 0.477 ; clk_div:clkdiv_inst|count_1Mhz[3] ; clk_div:clkdiv_inst|clock_1Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 0.000 ; 0.048 ; 0.711 ;; 0.600 ; clk_div:clkdiv_inst|count_1Mhz[4] ; clk_div:clkdiv_inst|clock_1Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 0.000 ; 0.048 ; 0.834 ;; 0.675 ; clk_div:clkdiv_inst|count_1Mhz[1] ; clk_div:clkdiv_inst|count_1Mhz[1] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 0.000 ; 0.043 ; 0.904 ;; 0.677 ; clk_div:clkdiv_inst|count_1Mhz[2] ; clk_div:clkdiv_inst|clock_1Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 0.000 ; 0.048 ; 0.911 ;; 0.682 ; clk_div:clkdiv_inst|count_1Mhz[2] ; clk_div:clkdiv_inst|count_1Mhz[2] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 0.000 ; 0.043 ; 0.911 ;; 0.689 ; clk_div:clkdiv_inst|count_1Mhz[3] ; clk_div:clkdiv_inst|count_1Mhz[3] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 0.000 ; 0.043 ; 0.918 ;; 0.690 ; clk_div:clkdiv_inst|count_1Mhz[4] ; clk_div:clkdiv_inst|count_1Mhz[4] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 0.000 ; 0.043 ; 0.919 ;; 0.700 ; clk_div:clkdiv_inst|count_1Mhz[0] ; clk_div:clkdiv_inst|count_1Mhz[0] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 0.000 ; 0.043 ; 0.929 ;; 0.987 ; clk_div:clkdiv_inst|count_1Mhz[1] ; clk_div:clkdiv_inst|count_1Mhz[2] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 0.000 ; 0.048 ; 1.221 ;; 0.999 ; clk_div:clkdiv_inst|count_1Mhz[0] ; clk_div:clkdiv_inst|count_1Mhz[1] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 0.000 ; 0.048 ; 1.233 ;; 1.001 ; clk_div:clkdiv_inst|count_1Mhz[3] ; clk_div:clkdiv_inst|count_1Mhz[4] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 0.000 ; 0.048 ; 1.235 ;; 1.004 ; clk_div:clkdiv_inst|count_1Mhz[0] ; clk_div:clkdiv_inst|count_1Mhz[2] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 0.000 ; 0.048 ; 1.238 ;; 1.004 ; clk_div:clkdiv_inst|count_1Mhz[2] ; clk_div:clkdiv_inst|count_1Mhz[3] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 0.000 ; 0.048 ; 1.238 ;; 1.009 ; clk_div:clkdiv_inst|count_1Mhz[2] ; clk_div:clkdiv_inst|count_1Mhz[4] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 0.000 ; 0.048 ; 1.243 ;; 1.108 ; clk_div:clkdiv_inst|count_1Mhz[1] ; clk_div:clkdiv_inst|count_1Mhz[3] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 0.000 ; 0.048 ; 1.342 ;; 1.113 ; clk_div:clkdiv_inst|count_1Mhz[1] ; clk_div:clkdiv_inst|count_1Mhz[4] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 0.000 ; 0.048 ; 1.347 ;; 1.125 ; clk_div:clkdiv_inst|count_1Mhz[0] ; clk_div:clkdiv_inst|count_1Mhz[3] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 0.000 ; 0.048 ; 1.359 ;; 1.130 ; clk_div:clkdiv_inst|count_1Mhz[0] ; clk_div:clkdiv_inst|count_1Mhz[4] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 0.000 ; 0.048 ; 1.364 ;; 1.182 ; clk_div:clkdiv_inst|count_1Mhz[3] ; clk_div:clkdiv_inst|count_1Mhz[2] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 0.000 ; 0.048 ; 1.416 ;; 1.182 ; clk_div:clkdiv_inst|count_1Mhz[3] ; clk_div:clkdiv_inst|count_1Mhz[1] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 0.000 ; 0.048 ; 1.416 ;; 1.182 ; clk_div:clkdiv_inst|count_1Mhz[3] ; clk_div:clkdiv_inst|count_1Mhz[0] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 0.000 ; 0.048 ; 1.416 ;; 1.306 ; clk_div:clkdiv_inst|count_1Mhz[4] ; clk_div:clkdiv_inst|count_1Mhz[3] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 0.000 ; 0.048 ; 1.540 ;; 1.306 ; clk_div:clkdiv_inst|count_1Mhz[4] ; clk_div:clkdiv_inst|count_1Mhz[2] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 0.000 ; 0.048 ; 1.540 ;; 1.306 ; clk_div:clkdiv_inst|count_1Mhz[4] ; clk_div:clkdiv_inst|count_1Mhz[1] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 0.000 ; 0.048 ; 1.540 ;; 1.306 ; clk_div:clkdiv_inst|count_1Mhz[4] ; clk_div:clkdiv_inst|count_1Mhz[0] ; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 0.000 ; 0.048 ; 1.540 ;+-------+-----------------------------------+------------------------------------+-------------------------------------+-------------------------------------+--------------+------------+------------++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Recovery: 'ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set' ;+--------+-----------+--------------------------------------------------+--------------+-------------------------------------------------+--------------+------------+------------+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;+--------+-----------+--------------------------------------------------+--------------+-------------------------------------------------+--------------+------------+------------+; -2.384 ; ps2_read ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_ready ; CLOCK_50 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set ; 1.000 ; -1.538 ; 1.844 ;+--------+-----------+--------------------------------------------------+--------------+-------------------------------------------------+--------------+------------+------------++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Removal: 'ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set' ;+-------+-----------+--------------------------------------------------+--------------+-------------------------------------------------+--------------+------------+------------+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;+-------+-----------+--------------------------------------------------+--------------+-------------------------------------------------+--------------+------------+------------+; 2.874 ; ps2_read ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_ready ; CLOCK_50 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set ; 0.000 ; -1.344 ; 1.736 ;+-------+-----------+--------------------------------------------------+--------------+-------------------------------------------------+--------------+------------+------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Minimum Pulse Width: 'SW[15]' ;+--------+--------------+----------------+------------+--------+------------+---------------------------------------------------------------------------------------------------------------+; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;+--------+--------------+----------------+------------+--------+------------+---------------------------------------------------------------------------------------------------------------+; -3.000 ; 1.000 ; 4.000 ; Port Rate ; SW[15] ; Rise ; SW[15] ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; SW[15] ; Rise ; charram:cram|altsyncram:altsyncram_component|altsyncram_l4o1:auto_generated|ram_block1a0~porta_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; SW[15] ; Rise ; charram:cram|altsyncram:altsyncram_component|altsyncram_l4o1:auto_generated|ram_block1a0~porta_datain_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; SW[15] ; Rise ; charram:cram|altsyncram:altsyncram_component|altsyncram_l4o1:auto_generated|ram_block1a0~porta_we_reg ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; SW[15] ; Rise ; charram:cram|altsyncram:altsyncram_component|altsyncram_l4o1:auto_generated|ram_block1a4~porta_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; SW[15] ; Rise ; charram:cram|altsyncram:altsyncram_component|altsyncram_l4o1:auto_generated|ram_block1a4~porta_datain_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; SW[15] ; Rise ; charram:cram|altsyncram:altsyncram_component|altsyncram_l4o1:auto_generated|ram_block1a4~porta_we_reg ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; SW[15] ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a0~porta_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; SW[15] ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a0~porta_datain_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; SW[15] ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a0~porta_we_reg ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; SW[15] ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a1~porta_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; SW[15] ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a1~porta_datain_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; SW[15] ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a1~porta_we_reg ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; SW[15] ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a2~porta_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; SW[15] ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a2~porta_datain_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; SW[15] ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a2~porta_we_reg ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; SW[15] ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a3~porta_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; SW[15] ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a3~porta_datain_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; SW[15] ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a3~porta_we_reg ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; SW[15] ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a4~porta_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; SW[15] ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a4~porta_datain_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; SW[15] ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a4~porta_we_reg ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; SW[15] ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a5~porta_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; SW[15] ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a5~porta_datain_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; SW[15] ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a5~porta_we_reg ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; SW[15] ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a6~porta_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; SW[15] ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a6~porta_datain_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; SW[15] ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a6~porta_we_reg ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; SW[15] ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a7~porta_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; SW[15] ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a7~porta_datain_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; SW[15] ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a7~porta_we_reg ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|DI_Reg[0] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|DI_Reg[1] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|DI_Reg[2] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|DI_Reg[3] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|DI_Reg[4] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|DI_Reg[5] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|DI_Reg[6] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|DI_Reg[7] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|IORQ_n ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|MREQ_n ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|RD_n ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|ACC[0] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|ACC[1] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|ACC[2] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|ACC[3] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|ACC[4] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|ACC[5] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|ACC[6] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|ACC[7] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|ALU_Op_r[0] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|ALU_Op_r[1] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|ALU_Op_r[2] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|ALU_Op_r[3] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|A[0] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|A[10] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|A[11] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|A[12] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|A[13] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|A[14] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|A[15] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|A[1] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|A[2] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|A[3] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|A[4] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|A[5] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|A[6] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|A[7] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|A[8] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|A[9] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|Alternate ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|Ap[0] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|Ap[1] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|Ap[2] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|Ap[3] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|Ap[4] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|Ap[5] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|Ap[6] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|Ap[7] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|Arith16_r ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|BTR_r ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|BusA[0] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|BusA[1] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|BusA[2] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|BusA[3] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|BusA[4] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|BusA[5] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|BusA[6] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|BusA[7] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|BusB[0] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|BusB[1] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|BusB[2] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|BusB[3] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|BusB[4] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|BusB[5] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|BusB[6] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|BusB[7] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|DO[0] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|DO[1] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; SW[15] ; Rise ; T80se:z80_inst|T80:u0|DO[2] ;+--------+--------------+----------------+------------+--------+------------+---------------------------------------------------------------------------------------------------------------++-----------------------------------------------------------------------------------------------------------------------+; Minimum Pulse Width: 'CLOCK_50' ;+--------+--------------+----------------+------------+----------+------------+-----------------------------------------+; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;+--------+--------------+----------------+------------+----------+------------+-----------------------------------------+; -3.000 ; 1.000 ; 4.000 ; Port Rate ; CLOCK_50 ; Rise ; CLOCK_50 ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|LCD_EN ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|LCD_ON ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|LCD_RS ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|char_count_sig[0] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|char_count_sig[1] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|char_count_sig[2] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|char_count_sig[3] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|char_count_sig[4] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|clk_400hz_enable ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|clk_count_400hz[0] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|clk_count_400hz[10] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|clk_count_400hz[11] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|clk_count_400hz[12] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|clk_count_400hz[13] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|clk_count_400hz[14] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|clk_count_400hz[15] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|clk_count_400hz[16] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|clk_count_400hz[17] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|clk_count_400hz[18] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|clk_count_400hz[19] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|clk_count_400hz[1] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|clk_count_400hz[2] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|clk_count_400hz[3] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|clk_count_400hz[4] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|clk_count_400hz[5] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|clk_count_400hz[6] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|clk_count_400hz[7] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|clk_count_400hz[8] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|clk_count_400hz[9] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|data_bus_value[0] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|data_bus_value[1] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|data_bus_value[2] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|data_bus_value[3] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|data_bus_value[4] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|data_bus_value[5] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|data_bus_value[6] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|data_bus_value[7] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|next_command.display_clear ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|next_command.display_off ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|next_command.display_on ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|next_command.func_set ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|next_command.line2 ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|next_command.mode_set ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|next_command.print_string ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|next_command.reset2 ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|next_command.reset3 ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|next_command.return_home ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|state.display_clear ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|state.display_off ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|state.display_on ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|state.drop_LCD_EN ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|state.func_set ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|state.hold ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|state.line2 ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|state.mode_set ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|state.print_string ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|state.reset1 ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|state.reset2 ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|state.reset3 ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; LCD:lcd_inst|state.return_home ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; \random:rand_temp[0] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; \random:rand_temp[10] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; \random:rand_temp[11] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; \random:rand_temp[12] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; \random:rand_temp[13] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; \random:rand_temp[14] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; \random:rand_temp[15] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; \random:rand_temp[1] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; \random:rand_temp[2] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; \random:rand_temp[3] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; \random:rand_temp[4] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; \random:rand_temp[5] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; \random:rand_temp[6] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; \random:rand_temp[7] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; \random:rand_temp[8] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; \random:rand_temp[9] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; clk_div:clkdiv_inst|clock_10MHz ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; clk_div:clkdiv_inst|clock_10Mhz_int ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; clk_div:clkdiv_inst|clock_1KHz ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; clk_div:clkdiv_inst|clock_25MHz ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; clk_div:clkdiv_inst|clock_25Mhz_int ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; clk_div:clkdiv_inst|clock_357Mhz ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; clk_div:clkdiv_inst|clock_357Mhz_int ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; clk_div:clkdiv_inst|count_10Mhz[0] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; clk_div:clkdiv_inst|count_10Mhz[1] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; clk_div:clkdiv_inst|count_10Mhz[2] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; clk_div:clkdiv_inst|count_357Mhz[0] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; clk_div:clkdiv_inst|count_357Mhz[1] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; clk_div:clkdiv_inst|count_357Mhz[2] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; clk_div:clkdiv_inst|count_357Mhz[3] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; ps2_ascii_reg1[0] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; ps2_ascii_reg1[1] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; ps2_ascii_reg1[2] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; ps2_ascii_reg1[3] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; ps2_ascii_reg1[4] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; ps2_ascii_reg1[5] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; ps2_ascii_reg1[6] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; CLOCK_50 ; Rise ; ps2_ascii_reg1[7] ;+--------+--------------+----------------+------------+----------+------------+-----------------------------------------++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Minimum Pulse Width: 'clk_div:clkdiv_inst|clock_100Hz' ;+--------+--------------+----------------+------------+---------------------------------+------------+---------------------------------------------------------------------------------------------------------------+; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;+--------+--------------+----------------+------------+---------------------------------+------------+---------------------------------------------------------------------------------------------------------------+; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; charram:cram|altsyncram:altsyncram_component|altsyncram_l4o1:auto_generated|ram_block1a0~porta_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; charram:cram|altsyncram:altsyncram_component|altsyncram_l4o1:auto_generated|ram_block1a0~porta_datain_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; charram:cram|altsyncram:altsyncram_component|altsyncram_l4o1:auto_generated|ram_block1a0~porta_we_reg ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; charram:cram|altsyncram:altsyncram_component|altsyncram_l4o1:auto_generated|ram_block1a4~porta_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; charram:cram|altsyncram:altsyncram_component|altsyncram_l4o1:auto_generated|ram_block1a4~porta_datain_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; charram:cram|altsyncram:altsyncram_component|altsyncram_l4o1:auto_generated|ram_block1a4~porta_we_reg ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a0~porta_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a0~porta_datain_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a0~porta_we_reg ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a1~porta_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a1~porta_datain_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a1~porta_we_reg ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a2~porta_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a2~porta_datain_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a2~porta_we_reg ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a3~porta_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a3~porta_datain_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a3~porta_we_reg ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a4~porta_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a4~porta_datain_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a4~porta_we_reg ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a5~porta_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a5~porta_datain_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a5~porta_we_reg ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a6~porta_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a6~porta_datain_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a6~porta_we_reg ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a7~porta_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a7~porta_datain_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a7~porta_we_reg ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|DI_Reg[0] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|DI_Reg[1] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|DI_Reg[2] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|DI_Reg[3] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|DI_Reg[4] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|DI_Reg[5] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|DI_Reg[6] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|DI_Reg[7] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|IORQ_n ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|MREQ_n ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|RD_n ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|ACC[0] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|ACC[1] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|ACC[2] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|ACC[3] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|ACC[4] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|ACC[5] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|ACC[6] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|ACC[7] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|ALU_Op_r[0] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|ALU_Op_r[1] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|ALU_Op_r[2] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|ALU_Op_r[3] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|A[0] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|A[10] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|A[11] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|A[12] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|A[13] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|A[14] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|A[15] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|A[1] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|A[2] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|A[3] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|A[4] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|A[5] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|A[6] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|A[7] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|A[8] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|A[9] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|Alternate ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|Ap[0] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|Ap[1] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|Ap[2] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|Ap[3] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|Ap[4] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|Ap[5] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|Ap[6] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|Ap[7] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|Arith16_r ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|BTR_r ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|BusA[0] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|BusA[1] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|BusA[2] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|BusA[3] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|BusA[4] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|BusA[5] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|BusA[6] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|BusA[7] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|BusB[0] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|BusB[1] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|BusB[2] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|BusB[3] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|BusB[4] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|BusB[5] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|BusB[6] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|BusB[7] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|DO[0] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|DO[1] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|DO[2] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Hz ; Rise ; T80se:z80_inst|T80:u0|DO[3] ;+--------+--------------+----------------+------------+---------------------------------+------------+---------------------------------------------------------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Minimum Pulse Width: 'clk_div:clkdiv_inst|clock_25MHz' ;+--------+--------------+----------------+-----------------+---------------------------------+------------+---------------------------------------------------------------------------------------------------------------+; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;+--------+--------------+----------------+-----------------+---------------------------------+------------+---------------------------------------------------------------------------------------------------------------+; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; charram:cram|altsyncram:altsyncram_component|altsyncram_l4o1:auto_generated|ram_block1a0~portb_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; charram:cram|altsyncram:altsyncram_component|altsyncram_l4o1:auto_generated|ram_block1a4~portb_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a0~porta_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a1 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a10 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a10~porta_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a11 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a11~porta_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a12 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a12~porta_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a13 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a13~porta_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a14 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a14~porta_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a15 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a15~porta_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a1~porta_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a2 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a2~porta_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a3 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a3~porta_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a4 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a4~porta_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a5 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a5~porta_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a6 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a6~porta_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a7 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a7~porta_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a8 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a8~porta_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a9 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a9~porta_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a0~portb_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a1~portb_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a2~portb_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a3~portb_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a4~portb_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a5~portb_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a6~portb_address_reg0 ;; -2.693 ; 1.000 ; 3.693 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a7~portb_address_reg0 ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|address_reg_a[0] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|out_address_reg_a[0] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|blue_out[0] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|blue_out[1] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|blue_out[2] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|blue_out[3] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|h_count[0] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|h_count[1] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|h_count[2] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|h_count[3] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|h_count[4] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|h_count[5] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|h_count[6] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|h_count[7] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|h_count[8] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|h_count[9] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|horiz_sync ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|horiz_sync_out ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_column[0] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_column[1] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_column[2] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_column[3] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_column[4] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_column[5] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_column[6] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_column[7] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_column[8] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_column[9] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_row[0] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_row[1] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_row[2] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_row[3] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_row[4] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_row[5] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_row[6] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_row[7] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_row[8] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|v_count[0] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|v_count[1] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|v_count[2] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|v_count[3] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|v_count[4] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|v_count[5] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|v_count[6] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|v_count[7] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|v_count[8] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|v_count[9] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|vert_sync ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|vert_sync_out ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|video_on_h ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; video:video_inst|VGA_SYNC:vga_sync_inst|video_on_v ;; 0.183 ; 0.418 ; 0.235 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a10~porta_address_reg0 ;; 0.183 ; 0.418 ; 0.235 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a15~porta_address_reg0 ;; 0.183 ; 0.418 ; 0.235 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a6~porta_address_reg0 ;; 0.183 ; 0.418 ; 0.235 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a8~porta_address_reg0 ;; 0.184 ; 0.419 ; 0.235 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a14~porta_address_reg0 ;; 0.184 ; 0.419 ; 0.235 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a1~porta_address_reg0 ;; 0.184 ; 0.419 ; 0.235 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_25MHz ; Rise ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a3~porta_address_reg0 ;+--------+--------------+----------------+-----------------+---------------------------------+------------+---------------------------------------------------------------------------------------------------------------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Minimum Pulse Width: 'ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered' ;+--------+--------------+----------------+------------------+-------------------------------------------------------------+------------+--------------------------------------------------------------+; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;+--------+--------------+----------------+------------------+-------------------------------------------------------------+------------+--------------------------------------------------------------+; -1.285 ; 1.000 ; 2.285 ; Min Period ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[0] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[1] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[2] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[3] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[4] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[5] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[6] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[7] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[8] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[0] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[1] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[2] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[3] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[4] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[5] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[6] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[7] ;; 0.282 ; 0.502 ; 0.220 ; High Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ;; 0.282 ; 0.502 ; 0.220 ; High Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ;; 0.282 ; 0.502 ; 0.220 ; High Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ;; 0.282 ; 0.502 ; 0.220 ; High Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ;; 0.282 ; 0.502 ; 0.220 ; High Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ;; 0.282 ; 0.502 ; 0.220 ; High Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[0] ;; 0.282 ; 0.502 ; 0.220 ; High Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[1] ;; 0.282 ; 0.502 ; 0.220 ; High Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[2] ;; 0.282 ; 0.502 ; 0.220 ; High Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[3] ;; 0.282 ; 0.502 ; 0.220 ; High Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[4] ;; 0.282 ; 0.502 ; 0.220 ; High Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[5] ;; 0.282 ; 0.502 ; 0.220 ; High Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[6] ;; 0.282 ; 0.502 ; 0.220 ; High Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[7] ;; 0.282 ; 0.502 ; 0.220 ; High Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[8] ;; 0.282 ; 0.502 ; 0.220 ; High Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set ;; 0.282 ; 0.502 ; 0.220 ; High Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[0] ;; 0.282 ; 0.502 ; 0.220 ; High Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[1] ;; 0.282 ; 0.502 ; 0.220 ; High Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[2] ;; 0.282 ; 0.502 ; 0.220 ; High Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[3] ;; 0.282 ; 0.502 ; 0.220 ; High Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[4] ;; 0.282 ; 0.502 ; 0.220 ; High Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[6] ;; 0.282 ; 0.502 ; 0.220 ; High Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[7] ;; 0.283 ; 0.503 ; 0.220 ; High Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[5] ;; 0.306 ; 0.494 ; 0.188 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[5] ;; 0.307 ; 0.495 ; 0.188 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0] ;; 0.307 ; 0.495 ; 0.188 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1] ;; 0.307 ; 0.495 ; 0.188 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2] ;; 0.307 ; 0.495 ; 0.188 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3] ;; 0.307 ; 0.495 ; 0.188 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR ;; 0.307 ; 0.495 ; 0.188 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[0] ;; 0.307 ; 0.495 ; 0.188 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[1] ;; 0.307 ; 0.495 ; 0.188 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[2] ;; 0.307 ; 0.495 ; 0.188 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[3] ;; 0.307 ; 0.495 ; 0.188 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[4] ;; 0.307 ; 0.495 ; 0.188 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[5] ;; 0.307 ; 0.495 ; 0.188 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[6] ;; 0.307 ; 0.495 ; 0.188 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[7] ;; 0.307 ; 0.495 ; 0.188 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[8] ;; 0.307 ; 0.495 ; 0.188 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set ;; 0.307 ; 0.495 ; 0.188 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[0] ;; 0.307 ; 0.495 ; 0.188 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[1] ;; 0.307 ; 0.495 ; 0.188 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[2] ;; 0.307 ; 0.495 ; 0.188 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[3] ;; 0.307 ; 0.495 ; 0.188 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[4] ;; 0.307 ; 0.495 ; 0.188 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[6] ;; 0.307 ; 0.495 ; 0.188 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[7] ;; 0.457 ; 0.457 ; 0.000 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2_kbd_inst|kbd_inst|keyboard_clk_filtered~clkctrl|inclk[0] ;; 0.457 ; 0.457 ; 0.000 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2_kbd_inst|kbd_inst|keyboard_clk_filtered~clkctrl|outclk ;; 0.459 ; 0.459 ; 0.000 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2_kbd_inst|kbd_inst|scan_code[5]|clk ;; 0.460 ; 0.460 ; 0.000 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2_kbd_inst|kbd_inst|INCNT[0]|clk ;; 0.460 ; 0.460 ; 0.000 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2_kbd_inst|kbd_inst|INCNT[1]|clk ;; 0.460 ; 0.460 ; 0.000 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2_kbd_inst|kbd_inst|INCNT[2]|clk ;; 0.460 ; 0.460 ; 0.000 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2_kbd_inst|kbd_inst|INCNT[3]|clk ;; 0.460 ; 0.460 ; 0.000 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2_kbd_inst|kbd_inst|READ_CHAR|clk ;; 0.460 ; 0.460 ; 0.000 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2_kbd_inst|kbd_inst|SHIFTIN[0]|clk ;; 0.460 ; 0.460 ; 0.000 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2_kbd_inst|kbd_inst|SHIFTIN[1]|clk ;; 0.460 ; 0.460 ; 0.000 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2_kbd_inst|kbd_inst|SHIFTIN[2]|clk ;; 0.460 ; 0.460 ; 0.000 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2_kbd_inst|kbd_inst|SHIFTIN[3]|clk ;; 0.460 ; 0.460 ; 0.000 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2_kbd_inst|kbd_inst|SHIFTIN[4]|clk ;; 0.460 ; 0.460 ; 0.000 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2_kbd_inst|kbd_inst|SHIFTIN[5]|clk ;; 0.460 ; 0.460 ; 0.000 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2_kbd_inst|kbd_inst|SHIFTIN[6]|clk ;; 0.460 ; 0.460 ; 0.000 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2_kbd_inst|kbd_inst|SHIFTIN[7]|clk ;; 0.460 ; 0.460 ; 0.000 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2_kbd_inst|kbd_inst|SHIFTIN[8]|clk ;; 0.460 ; 0.460 ; 0.000 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2_kbd_inst|kbd_inst|ready_set|clk ;; 0.460 ; 0.460 ; 0.000 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2_kbd_inst|kbd_inst|scan_code[0]|clk ;; 0.460 ; 0.460 ; 0.000 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2_kbd_inst|kbd_inst|scan_code[1]|clk ;; 0.460 ; 0.460 ; 0.000 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2_kbd_inst|kbd_inst|scan_code[2]|clk ;; 0.460 ; 0.460 ; 0.000 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2_kbd_inst|kbd_inst|scan_code[3]|clk ;; 0.460 ; 0.460 ; 0.000 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2_kbd_inst|kbd_inst|scan_code[4]|clk ;; 0.460 ; 0.460 ; 0.000 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2_kbd_inst|kbd_inst|scan_code[6]|clk ;; 0.460 ; 0.460 ; 0.000 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2_kbd_inst|kbd_inst|scan_code[7]|clk ;; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2_kbd_inst|kbd_inst|keyboard_clk_filtered|q ;; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2_kbd_inst|kbd_inst|keyboard_clk_filtered|q ;; 0.538 ; 0.538 ; 0.000 ; High Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2_kbd_inst|kbd_inst|INCNT[0]|clk ;; 0.538 ; 0.538 ; 0.000 ; High Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2_kbd_inst|kbd_inst|INCNT[1]|clk ;; 0.538 ; 0.538 ; 0.000 ; High Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2_kbd_inst|kbd_inst|INCNT[2]|clk ;; 0.538 ; 0.538 ; 0.000 ; High Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Rise ; ps2_kbd_inst|kbd_inst|INCNT[3]|clk ;+--------+--------------+----------------+------------------+-------------------------------------------------------------+------------+--------------------------------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------------+; Minimum Pulse Width: 'clk_div:clkdiv_inst|clock_25Mhz_int' ;+--------+--------------+----------------+------------------+-------------------------------------+------------+------------------------------------+; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;+--------+--------------+----------------+------------------+-------------------------------------+------------+------------------------------------+; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25Mhz_int ; Rise ; clk_div:clkdiv_inst|clock_1Mhz_int ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25Mhz_int ; Rise ; clk_div:clkdiv_inst|count_1Mhz[0] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25Mhz_int ; Rise ; clk_div:clkdiv_inst|count_1Mhz[1] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25Mhz_int ; Rise ; clk_div:clkdiv_inst|count_1Mhz[2] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25Mhz_int ; Rise ; clk_div:clkdiv_inst|count_1Mhz[3] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_25Mhz_int ; Rise ; clk_div:clkdiv_inst|count_1Mhz[4] ;; 0.272 ; 0.460 ; 0.188 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_25Mhz_int ; Rise ; clk_div:clkdiv_inst|clock_1Mhz_int ;; 0.272 ; 0.460 ; 0.188 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_25Mhz_int ; Rise ; clk_div:clkdiv_inst|count_1Mhz[0] ;; 0.272 ; 0.460 ; 0.188 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_25Mhz_int ; Rise ; clk_div:clkdiv_inst|count_1Mhz[1] ;; 0.272 ; 0.460 ; 0.188 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_25Mhz_int ; Rise ; clk_div:clkdiv_inst|count_1Mhz[2] ;; 0.272 ; 0.460 ; 0.188 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_25Mhz_int ; Rise ; clk_div:clkdiv_inst|count_1Mhz[3] ;; 0.272 ; 0.460 ; 0.188 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_25Mhz_int ; Rise ; clk_div:clkdiv_inst|count_1Mhz[4] ;; 0.316 ; 0.536 ; 0.220 ; High Pulse Width ; clk_div:clkdiv_inst|clock_25Mhz_int ; Rise ; clk_div:clkdiv_inst|clock_1Mhz_int ;; 0.316 ; 0.536 ; 0.220 ; High Pulse Width ; clk_div:clkdiv_inst|clock_25Mhz_int ; Rise ; clk_div:clkdiv_inst|count_1Mhz[0] ;; 0.316 ; 0.536 ; 0.220 ; High Pulse Width ; clk_div:clkdiv_inst|clock_25Mhz_int ; Rise ; clk_div:clkdiv_inst|count_1Mhz[1] ;; 0.316 ; 0.536 ; 0.220 ; High Pulse Width ; clk_div:clkdiv_inst|clock_25Mhz_int ; Rise ; clk_div:clkdiv_inst|count_1Mhz[2] ;; 0.316 ; 0.536 ; 0.220 ; High Pulse Width ; clk_div:clkdiv_inst|clock_25Mhz_int ; Rise ; clk_div:clkdiv_inst|count_1Mhz[3] ;; 0.316 ; 0.536 ; 0.220 ; High Pulse Width ; clk_div:clkdiv_inst|clock_25Mhz_int ; Rise ; clk_div:clkdiv_inst|count_1Mhz[4] ;; 0.425 ; 0.425 ; 0.000 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_25Mhz_int ; Rise ; clkdiv_inst|clock_1Mhz_int|clk ;; 0.425 ; 0.425 ; 0.000 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_25Mhz_int ; Rise ; clkdiv_inst|count_1Mhz[0]|clk ;; 0.425 ; 0.425 ; 0.000 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_25Mhz_int ; Rise ; clkdiv_inst|count_1Mhz[1]|clk ;; 0.425 ; 0.425 ; 0.000 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_25Mhz_int ; Rise ; clkdiv_inst|count_1Mhz[2]|clk ;; 0.425 ; 0.425 ; 0.000 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_25Mhz_int ; Rise ; clkdiv_inst|count_1Mhz[3]|clk ;; 0.425 ; 0.425 ; 0.000 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_25Mhz_int ; Rise ; clkdiv_inst|count_1Mhz[4]|clk ;; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk_div:clkdiv_inst|clock_25Mhz_int ; Rise ; clkdiv_inst|clock_25Mhz_int|q ;; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_25Mhz_int ; Rise ; clkdiv_inst|clock_25Mhz_int|q ;; 0.572 ; 0.572 ; 0.000 ; High Pulse Width ; clk_div:clkdiv_inst|clock_25Mhz_int ; Rise ; clkdiv_inst|clock_1Mhz_int|clk ;; 0.572 ; 0.572 ; 0.000 ; High Pulse Width ; clk_div:clkdiv_inst|clock_25Mhz_int ; Rise ; clkdiv_inst|count_1Mhz[0]|clk ;; 0.572 ; 0.572 ; 0.000 ; High Pulse Width ; clk_div:clkdiv_inst|clock_25Mhz_int ; Rise ; clkdiv_inst|count_1Mhz[1]|clk ;; 0.572 ; 0.572 ; 0.000 ; High Pulse Width ; clk_div:clkdiv_inst|clock_25Mhz_int ; Rise ; clkdiv_inst|count_1Mhz[2]|clk ;; 0.572 ; 0.572 ; 0.000 ; High Pulse Width ; clk_div:clkdiv_inst|clock_25Mhz_int ; Rise ; clkdiv_inst|count_1Mhz[3]|clk ;; 0.572 ; 0.572 ; 0.000 ; High Pulse Width ; clk_div:clkdiv_inst|clock_25Mhz_int ; Rise ; clkdiv_inst|count_1Mhz[4]|clk ;+--------+--------------+----------------+------------------+-------------------------------------+------------+------------------------------------++-----------------------------------------------------------------------------------------------------------------------------------------------------+; Minimum Pulse Width: 'clk_div:clkdiv_inst|clock_100Khz_int' ;+--------+--------------+----------------+------------------+--------------------------------------+------------+-------------------------------------+; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;+--------+--------------+----------------+------------------+--------------------------------------+------------+-------------------------------------+; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Khz_int ; Rise ; clk_div:clkdiv_inst|clock_10Khz_int ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Khz_int ; Rise ; clk_div:clkdiv_inst|count_10Khz[0] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Khz_int ; Rise ; clk_div:clkdiv_inst|count_10Khz[1] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_100Khz_int ; Rise ; clk_div:clkdiv_inst|count_10Khz[2] ;; 0.263 ; 0.451 ; 0.188 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_100Khz_int ; Rise ; clk_div:clkdiv_inst|clock_10Khz_int ;; 0.263 ; 0.451 ; 0.188 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_100Khz_int ; Rise ; clk_div:clkdiv_inst|count_10Khz[0] ;; 0.263 ; 0.451 ; 0.188 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_100Khz_int ; Rise ; clk_div:clkdiv_inst|count_10Khz[1] ;; 0.263 ; 0.451 ; 0.188 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_100Khz_int ; Rise ; clk_div:clkdiv_inst|count_10Khz[2] ;; 0.324 ; 0.544 ; 0.220 ; High Pulse Width ; clk_div:clkdiv_inst|clock_100Khz_int ; Rise ; clk_div:clkdiv_inst|clock_10Khz_int ;; 0.324 ; 0.544 ; 0.220 ; High Pulse Width ; clk_div:clkdiv_inst|clock_100Khz_int ; Rise ; clk_div:clkdiv_inst|count_10Khz[0] ;; 0.324 ; 0.544 ; 0.220 ; High Pulse Width ; clk_div:clkdiv_inst|clock_100Khz_int ; Rise ; clk_div:clkdiv_inst|count_10Khz[1] ;; 0.324 ; 0.544 ; 0.220 ; High Pulse Width ; clk_div:clkdiv_inst|clock_100Khz_int ; Rise ; clk_div:clkdiv_inst|count_10Khz[2] ;; 0.416 ; 0.416 ; 0.000 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_100Khz_int ; Rise ; clkdiv_inst|clock_10Khz_int|clk ;; 0.416 ; 0.416 ; 0.000 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_100Khz_int ; Rise ; clkdiv_inst|count_10Khz[0]|clk ;; 0.416 ; 0.416 ; 0.000 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_100Khz_int ; Rise ; clkdiv_inst|count_10Khz[1]|clk ;; 0.416 ; 0.416 ; 0.000 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_100Khz_int ; Rise ; clkdiv_inst|count_10Khz[2]|clk ;; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk_div:clkdiv_inst|clock_100Khz_int ; Rise ; clkdiv_inst|clock_100Khz_int|q ;; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_100Khz_int ; Rise ; clkdiv_inst|clock_100Khz_int|q ;; 0.580 ; 0.580 ; 0.000 ; High Pulse Width ; clk_div:clkdiv_inst|clock_100Khz_int ; Rise ; clkdiv_inst|clock_10Khz_int|clk ;; 0.580 ; 0.580 ; 0.000 ; High Pulse Width ; clk_div:clkdiv_inst|clock_100Khz_int ; Rise ; clkdiv_inst|count_10Khz[0]|clk ;; 0.580 ; 0.580 ; 0.000 ; High Pulse Width ; clk_div:clkdiv_inst|clock_100Khz_int ; Rise ; clkdiv_inst|count_10Khz[1]|clk ;; 0.580 ; 0.580 ; 0.000 ; High Pulse Width ; clk_div:clkdiv_inst|clock_100Khz_int ; Rise ; clkdiv_inst|count_10Khz[2]|clk ;+--------+--------------+----------------+------------------+--------------------------------------+------------+-------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------------+; Minimum Pulse Width: 'clk_div:clkdiv_inst|clock_10Khz_int' ;+--------+--------------+----------------+------------------+-------------------------------------+------------+------------------------------------+; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;+--------+--------------+----------------+------------------+-------------------------------------+------------+------------------------------------+; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_10Khz_int ; Rise ; clk_div:clkdiv_inst|clock_1Khz_int ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_10Khz_int ; Rise ; clk_div:clkdiv_inst|count_1Khz[0] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_10Khz_int ; Rise ; clk_div:clkdiv_inst|count_1Khz[1] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_10Khz_int ; Rise ; clk_div:clkdiv_inst|count_1Khz[2] ;; 0.274 ; 0.494 ; 0.220 ; High Pulse Width ; clk_div:clkdiv_inst|clock_10Khz_int ; Rise ; clk_div:clkdiv_inst|clock_1Khz_int ;; 0.274 ; 0.494 ; 0.220 ; High Pulse Width ; clk_div:clkdiv_inst|clock_10Khz_int ; Rise ; clk_div:clkdiv_inst|count_1Khz[0] ;; 0.274 ; 0.494 ; 0.220 ; High Pulse Width ; clk_div:clkdiv_inst|clock_10Khz_int ; Rise ; clk_div:clkdiv_inst|count_1Khz[1] ;; 0.274 ; 0.494 ; 0.220 ; High Pulse Width ; clk_div:clkdiv_inst|clock_10Khz_int ; Rise ; clk_div:clkdiv_inst|count_1Khz[2] ;; 0.315 ; 0.503 ; 0.188 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_10Khz_int ; Rise ; clk_div:clkdiv_inst|clock_1Khz_int ;; 0.315 ; 0.503 ; 0.188 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_10Khz_int ; Rise ; clk_div:clkdiv_inst|count_1Khz[0] ;; 0.315 ; 0.503 ; 0.188 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_10Khz_int ; Rise ; clk_div:clkdiv_inst|count_1Khz[1] ;; 0.315 ; 0.503 ; 0.188 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_10Khz_int ; Rise ; clk_div:clkdiv_inst|count_1Khz[2] ;; 0.468 ; 0.468 ; 0.000 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_10Khz_int ; Rise ; clkdiv_inst|clock_1Khz_int|clk ;; 0.468 ; 0.468 ; 0.000 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_10Khz_int ; Rise ; clkdiv_inst|count_1Khz[0]|clk ;; 0.468 ; 0.468 ; 0.000 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_10Khz_int ; Rise ; clkdiv_inst|count_1Khz[1]|clk ;; 0.468 ; 0.468 ; 0.000 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_10Khz_int ; Rise ; clkdiv_inst|count_1Khz[2]|clk ;; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk_div:clkdiv_inst|clock_10Khz_int ; Rise ; clkdiv_inst|clock_10Khz_int|q ;; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_10Khz_int ; Rise ; clkdiv_inst|clock_10Khz_int|q ;; 0.530 ; 0.530 ; 0.000 ; High Pulse Width ; clk_div:clkdiv_inst|clock_10Khz_int ; Rise ; clkdiv_inst|clock_1Khz_int|clk ;; 0.530 ; 0.530 ; 0.000 ; High Pulse Width ; clk_div:clkdiv_inst|clock_10Khz_int ; Rise ; clkdiv_inst|count_1Khz[0]|clk ;; 0.530 ; 0.530 ; 0.000 ; High Pulse Width ; clk_div:clkdiv_inst|clock_10Khz_int ; Rise ; clkdiv_inst|count_1Khz[1]|clk ;; 0.530 ; 0.530 ; 0.000 ; High Pulse Width ; clk_div:clkdiv_inst|clock_10Khz_int ; Rise ; clkdiv_inst|count_1Khz[2]|clk ;+--------+--------------+----------------+------------------+-------------------------------------+------------+------------------------------------++---------------------------------------------------------------------------------------------------------------------------------------------------+; Minimum Pulse Width: 'clk_div:clkdiv_inst|clock_1Khz_int' ;+--------+--------------+----------------+------------------+------------------------------------+------------+-------------------------------------+; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;+--------+--------------+----------------+------------------+------------------------------------+------------+-------------------------------------+; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_1Khz_int ; Rise ; clk_div:clkdiv_inst|clock_100hz_int ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_1Khz_int ; Rise ; clk_div:clkdiv_inst|count_100hz[0] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_1Khz_int ; Rise ; clk_div:clkdiv_inst|count_100hz[1] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_1Khz_int ; Rise ; clk_div:clkdiv_inst|count_100hz[2] ;; 0.271 ; 0.491 ; 0.220 ; High Pulse Width ; clk_div:clkdiv_inst|clock_1Khz_int ; Rise ; clk_div:clkdiv_inst|clock_100hz_int ;; 0.271 ; 0.491 ; 0.220 ; High Pulse Width ; clk_div:clkdiv_inst|clock_1Khz_int ; Rise ; clk_div:clkdiv_inst|count_100hz[0] ;; 0.271 ; 0.491 ; 0.220 ; High Pulse Width ; clk_div:clkdiv_inst|clock_1Khz_int ; Rise ; clk_div:clkdiv_inst|count_100hz[1] ;; 0.271 ; 0.491 ; 0.220 ; High Pulse Width ; clk_div:clkdiv_inst|clock_1Khz_int ; Rise ; clk_div:clkdiv_inst|count_100hz[2] ;; 0.319 ; 0.507 ; 0.188 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_1Khz_int ; Rise ; clk_div:clkdiv_inst|clock_100hz_int ;; 0.319 ; 0.507 ; 0.188 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_1Khz_int ; Rise ; clk_div:clkdiv_inst|count_100hz[0] ;; 0.319 ; 0.507 ; 0.188 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_1Khz_int ; Rise ; clk_div:clkdiv_inst|count_100hz[1] ;; 0.319 ; 0.507 ; 0.188 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_1Khz_int ; Rise ; clk_div:clkdiv_inst|count_100hz[2] ;; 0.472 ; 0.472 ; 0.000 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_1Khz_int ; Rise ; clkdiv_inst|clock_100hz_int|clk ;; 0.472 ; 0.472 ; 0.000 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_1Khz_int ; Rise ; clkdiv_inst|count_100hz[0]|clk ;; 0.472 ; 0.472 ; 0.000 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_1Khz_int ; Rise ; clkdiv_inst|count_100hz[1]|clk ;; 0.472 ; 0.472 ; 0.000 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_1Khz_int ; Rise ; clkdiv_inst|count_100hz[2]|clk ;; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk_div:clkdiv_inst|clock_1Khz_int ; Rise ; clkdiv_inst|clock_1Khz_int|q ;; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_1Khz_int ; Rise ; clkdiv_inst|clock_1Khz_int|q ;; 0.527 ; 0.527 ; 0.000 ; High Pulse Width ; clk_div:clkdiv_inst|clock_1Khz_int ; Rise ; clkdiv_inst|clock_100hz_int|clk ;; 0.527 ; 0.527 ; 0.000 ; High Pulse Width ; clk_div:clkdiv_inst|clock_1Khz_int ; Rise ; clkdiv_inst|count_100hz[0]|clk ;; 0.527 ; 0.527 ; 0.000 ; High Pulse Width ; clk_div:clkdiv_inst|clock_1Khz_int ; Rise ; clkdiv_inst|count_100hz[1]|clk ;; 0.527 ; 0.527 ; 0.000 ; High Pulse Width ; clk_div:clkdiv_inst|clock_1Khz_int ; Rise ; clkdiv_inst|count_100hz[2]|clk ;+--------+--------------+----------------+------------------+------------------------------------+------------+-------------------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------+; Minimum Pulse Width: 'clk_div:clkdiv_inst|clock_1Mhz_int' ;+--------+--------------+----------------+------------------+------------------------------------+------------+--------------------------------------+; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;+--------+--------------+----------------+------------------+------------------------------------+------------+--------------------------------------+; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_1Mhz_int ; Rise ; clk_div:clkdiv_inst|clock_100Khz_int ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_1Mhz_int ; Rise ; clk_div:clkdiv_inst|count_100Khz[0] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_1Mhz_int ; Rise ; clk_div:clkdiv_inst|count_100Khz[1] ;; -1.285 ; 1.000 ; 2.285 ; Min Period ; clk_div:clkdiv_inst|clock_1Mhz_int ; Rise ; clk_div:clkdiv_inst|count_100Khz[2] ;; 0.271 ; 0.491 ; 0.220 ; High Pulse Width ; clk_div:clkdiv_inst|clock_1Mhz_int ; Rise ; clk_div:clkdiv_inst|clock_100Khz_int ;; 0.271 ; 0.491 ; 0.220 ; High Pulse Width ; clk_div:clkdiv_inst|clock_1Mhz_int ; Rise ; clk_div:clkdiv_inst|count_100Khz[0] ;; 0.271 ; 0.491 ; 0.220 ; High Pulse Width ; clk_div:clkdiv_inst|clock_1Mhz_int ; Rise ; clk_div:clkdiv_inst|count_100Khz[1] ;; 0.271 ; 0.491 ; 0.220 ; High Pulse Width ; clk_div:clkdiv_inst|clock_1Mhz_int ; Rise ; clk_div:clkdiv_inst|count_100Khz[2] ;; 0.319 ; 0.507 ; 0.188 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_1Mhz_int ; Rise ; clk_div:clkdiv_inst|clock_100Khz_int ;; 0.319 ; 0.507 ; 0.188 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_1Mhz_int ; Rise ; clk_div:clkdiv_inst|count_100Khz[0] ;; 0.319 ; 0.507 ; 0.188 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_1Mhz_int ; Rise ; clk_div:clkdiv_inst|count_100Khz[1] ;; 0.319 ; 0.507 ; 0.188 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_1Mhz_int ; Rise ; clk_div:clkdiv_inst|count_100Khz[2] ;; 0.472 ; 0.472 ; 0.000 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_1Mhz_int ; Rise ; clkdiv_inst|clock_100Khz_int|clk ;; 0.472 ; 0.472 ; 0.000 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_1Mhz_int ; Rise ; clkdiv_inst|count_100Khz[0]|clk ;; 0.472 ; 0.472 ; 0.000 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_1Mhz_int ; Rise ; clkdiv_inst|count_100Khz[1]|clk ;; 0.472 ; 0.472 ; 0.000 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_1Mhz_int ; Rise ; clkdiv_inst|count_100Khz[2]|clk ;; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk_div:clkdiv_inst|clock_1Mhz_int ; Rise ; clkdiv_inst|clock_1Mhz_int|q ;; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk_div:clkdiv_inst|clock_1Mhz_int ; Rise ; clkdiv_inst|clock_1Mhz_int|q ;; 0.527 ; 0.527 ; 0.000 ; High Pulse Width ; clk_div:clkdiv_inst|clock_1Mhz_int ; Rise ; clkdiv_inst|clock_100Khz_int|clk ;; 0.527 ; 0.527 ; 0.000 ; High Pulse Width ; clk_div:clkdiv_inst|clock_1Mhz_int ; Rise ; clkdiv_inst|count_100Khz[0]|clk ;; 0.527 ; 0.527 ; 0.000 ; High Pulse Width ; clk_div:clkdiv_inst|clock_1Mhz_int ; Rise ; clkdiv_inst|count_100Khz[1]|clk ;; 0.527 ; 0.527 ; 0.000 ; High Pulse Width ; clk_div:clkdiv_inst|clock_1Mhz_int ; Rise ; clkdiv_inst|count_100Khz[2]|clk ;+--------+--------------+----------------+------------------+------------------------------------+------------+--------------------------------------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Minimum Pulse Width: 'ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set' ;+--------+--------------+----------------+------------------+-------------------------------------------------+------------+--------------------------------------------------+; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;+--------+--------------+----------------+------------------+-------------------------------------------------+------------+--------------------------------------------------+; -1.285 ; 1.000 ; 2.285 ; Min Period ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_ready ;; 0.261 ; 0.481 ; 0.220 ; High Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_ready ;; 0.329 ; 0.517 ; 0.188 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_ready ;; 0.482 ; 0.482 ; 0.000 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set ; Rise ; ps2_kbd_inst|kbd_inst|scan_ready|clk ;; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set ; Rise ; ps2_kbd_inst|kbd_inst|ready_set|q ;; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set ; Rise ; ps2_kbd_inst|kbd_inst|ready_set|q ;; 0.517 ; 0.517 ; 0.000 ; High Pulse Width ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set ; Rise ; ps2_kbd_inst|kbd_inst|scan_ready|clk ;+--------+--------------+----------------+------------------+-------------------------------------------------+------------+--------------------------------------------------++-----------------------------------------------------------------------------------------------------------------------------+; Minimum Pulse Width: 'T80se:z80_inst|MREQ_n' ;+-------+--------------+----------------+------------------+-----------------------+------------+-----------------------------+; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;+-------+--------------+----------------+------------------+-----------------------+------------+-----------------------------+; 0.261 ; 0.261 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[0][7] ;; 0.264 ; 0.264 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[0][4] ;; 0.268 ; 0.268 ; 0.000 ; High Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[0][4]|datac ;; 0.268 ; 0.268 ; 0.000 ; High Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[0][7]|datac ;; 0.274 ; 0.274 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[0][1] ;; 0.274 ; 0.274 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[0][5] ;; 0.275 ; 0.275 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[0][3] ;; 0.281 ; 0.281 ; 0.000 ; High Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[0][1]|datac ;; 0.281 ; 0.281 ; 0.000 ; High Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[0][5]|datac ;; 0.282 ; 0.282 ; 0.000 ; High Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[0][3]|datac ;; 0.282 ; 0.282 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[8][2] ;; 0.282 ; 0.282 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[8][6] ;; 0.287 ; 0.287 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[8][4] ;; 0.289 ; 0.289 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[8][7] ;; 0.301 ; 0.301 ; 0.000 ; High Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[8][2]|datab ;; 0.301 ; 0.301 ; 0.000 ; High Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[8][6]|datab ;; 0.302 ; 0.302 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[0][2] ;; 0.302 ; 0.302 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[0][6] ;; 0.304 ; 0.304 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[15][7] ;; 0.309 ; 0.309 ; 0.000 ; High Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[8][0]|datab ;; 0.313 ; 0.313 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[8][0] ;; 0.316 ; 0.316 ; 0.000 ; High Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[8][4]|datad ;; 0.318 ; 0.318 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[8][1] ;; 0.318 ; 0.318 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[8][3] ;; 0.318 ; 0.318 ; 0.000 ; High Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[8][7]|datad ;; 0.322 ; 0.322 ; 0.000 ; High Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[8][5]|dataa ;; 0.323 ; 0.323 ; 0.000 ; High Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; Decoder0~30|combout ;; 0.327 ; 0.327 ; 0.000 ; High Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; Decoder0~34|combout ;; 0.331 ; 0.331 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[15][3] ;; 0.333 ; 0.333 ; 0.000 ; High Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[15][7]|datad ;; 0.334 ; 0.334 ; 0.000 ; High Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[0][2]|dataa ;; 0.334 ; 0.334 ; 0.000 ; High Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[0][6]|dataa ;; 0.335 ; 0.335 ; 0.000 ; High Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[0][0]|dataa ;; 0.336 ; 0.336 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[22][4] ;; 0.338 ; 0.338 ; 0.000 ; High Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[15][3]|datac ;; 0.338 ; 0.338 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[8][5] ;; 0.343 ; 0.343 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[15][5] ;; 0.346 ; 0.346 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[14][0] ;; 0.347 ; 0.347 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[15][0] ;; 0.347 ; 0.347 ; 0.000 ; High Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[8][1]|datad ;; 0.347 ; 0.347 ; 0.000 ; High Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[8][3]|datad ;; 0.350 ; 0.350 ; 0.000 ; High Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[15][5]|datac ;; 0.351 ; 0.351 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[0][0] ;; 0.352 ; 0.352 ; 0.000 ; High Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; Decoder0~30|datad ;; 0.354 ; 0.354 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[22][0] ;; 0.355 ; 0.355 ; 0.000 ; High Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[22][6]|datab ;; 0.356 ; 0.356 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; Decoder0~25clkctrl|inclk[0] ;; 0.356 ; 0.356 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; Decoder0~25clkctrl|outclk ;; 0.356 ; 0.356 ; 0.000 ; High Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; Decoder0~34|datad ;; 0.356 ; 0.356 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[11][3] ;; 0.357 ; 0.357 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[15][4] ;; 0.359 ; 0.359 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[15][6] ;; 0.359 ; 0.359 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[22][6] ;; 0.359 ; 0.359 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[5][1]|datad ;; 0.359 ; 0.359 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[5][5]|datad ;; 0.360 ; 0.360 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[5][3]|datad ;; 0.361 ; 0.361 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[14][2] ;; 0.361 ; 0.361 ; 0.000 ; High Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[15][2]|datab ;; 0.361 ; 0.361 ; 0.000 ; High Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[22][0]|datac ;; 0.361 ; 0.361 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[5][4]|datad ;; 0.362 ; 0.362 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[5][0]|datad ;; 0.362 ; 0.362 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[5][2]|datad ;; 0.362 ; 0.362 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[5][6]|datad ;; 0.363 ; 0.363 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[5][7]|datad ;; 0.365 ; 0.365 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[15][2] ;; 0.366 ; 0.366 ; 0.000 ; High Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[11][3]|datab ;; 0.366 ; 0.366 ; 0.000 ; High Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[15][0]|datab ;; 0.367 ; 0.367 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[24][3] ;; 0.367 ; 0.367 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[24][4] ;; 0.368 ; 0.368 ; 0.000 ; High Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[22][4]|dataa ;; 0.368 ; 0.368 ; 0.000 ; High Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[22][7]|dataa ;; 0.369 ; 0.369 ; 0.000 ; High Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[22][2]|dataa ;; 0.370 ; 0.370 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[24][6] ;; 0.371 ; 0.371 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[11][5] ;; 0.373 ; 0.373 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[24][5] ;; 0.373 ; 0.373 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[24][7] ;; 0.375 ; 0.375 ; 0.000 ; High Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[14][2]|dataa ;; 0.377 ; 0.377 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[12][4] ;; 0.378 ; 0.378 ; 0.000 ; High Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[11][5]|datac ;; 0.378 ; 0.378 ; 0.000 ; High Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[14][0]|dataa ;; 0.378 ; 0.378 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[22][5] ;; 0.379 ; 0.379 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[15][1] ;; 0.379 ; 0.379 ; 0.000 ; High Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[22][1]|datab ;; 0.380 ; 0.380 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[11][0] ;; 0.380 ; 0.380 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[22][3] ;; 0.383 ; 0.383 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[14][1] ;; 0.383 ; 0.383 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[22][1] ;; 0.384 ; 0.384 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[14][3] ;; 0.384 ; 0.384 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[14][5] ;; 0.384 ; 0.384 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[22][7] ;; 0.385 ; 0.385 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[12][2] ;; 0.385 ; 0.385 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[14][4] ;; 0.385 ; 0.385 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[14][6] ;; 0.385 ; 0.385 ; 0.000 ; High Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[15][1]|dataa ;; 0.385 ; 0.385 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[22][2] ;; 0.385 ; 0.385 ; 0.000 ; High Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[22][3]|datac ;; 0.385 ; 0.385 ; 0.000 ; High Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; lcdvram[22][5]|datac ;; 0.387 ; 0.387 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[3][5] ;; 0.387 ; 0.387 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Fall ; lcdvram[3][7] ;; 0.388 ; 0.388 ; 0.000 ; Low Pulse Width ; T80se:z80_inst|MREQ_n ; Rise ; Decoder0~28clkctrl|inclk[0] ;+-------+--------------+----------------+------------------+-----------------------+------------+-----------------------------++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Setup Times ;+-------------+-------------------------------------------------------------+--------+--------+------------+-------------------------------------------------------------+; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;+-------------+-------------------------------------------------------------+--------+--------+------------+-------------------------------------------------------------+; PS2_CLK ; CLOCK_50 ; 2.341 ; 2.857 ; Rise ; CLOCK_50 ;; SW[*] ; CLOCK_50 ; 4.575 ; 5.177 ; Rise ; CLOCK_50 ;; SW[14] ; CLOCK_50 ; 3.320 ; 3.934 ; Rise ; CLOCK_50 ;; SW[17] ; CLOCK_50 ; 4.575 ; 5.177 ; Rise ; CLOCK_50 ;; KEY[*] ; SW[15] ; 2.193 ; 2.664 ; Rise ; SW[15] ;; KEY[0] ; SW[15] ; 2.193 ; 2.664 ; Rise ; SW[15] ;; KEY[1] ; SW[15] ; 1.871 ; 2.463 ; Rise ; SW[15] ;; KEY[2] ; SW[15] ; 1.154 ; 1.705 ; Rise ; SW[15] ;; KEY[3] ; SW[15] ; 1.932 ; 2.453 ; Rise ; SW[15] ;; SRAM_DQ[*] ; SW[15] ; 1.842 ; 2.503 ; Rise ; SW[15] ;; SRAM_DQ[0] ; SW[15] ; 1.842 ; 2.503 ; Rise ; SW[15] ;; SRAM_DQ[1] ; SW[15] ; 1.636 ; 2.251 ; Rise ; SW[15] ;; SRAM_DQ[2] ; SW[15] ; 0.686 ; 1.302 ; Rise ; SW[15] ;; SRAM_DQ[3] ; SW[15] ; 1.154 ; 1.797 ; Rise ; SW[15] ;; SRAM_DQ[4] ; SW[15] ; 0.746 ; 1.365 ; Rise ; SW[15] ;; SRAM_DQ[5] ; SW[15] ; 1.501 ; 2.159 ; Rise ; SW[15] ;; SRAM_DQ[6] ; SW[15] ; 0.705 ; 1.301 ; Rise ; SW[15] ;; SRAM_DQ[7] ; SW[15] ; 0.875 ; 1.428 ; Rise ; SW[15] ;; SW[*] ; SW[15] ; 2.796 ; 3.412 ; Rise ; SW[15] ;; SW[0] ; SW[15] ; 2.796 ; 3.412 ; Rise ; SW[15] ;; SW[1] ; SW[15] ; 1.746 ; 2.442 ; Rise ; SW[15] ;; SW[2] ; SW[15] ; 2.380 ; 2.970 ; Rise ; SW[15] ;; SW[3] ; SW[15] ; 2.125 ; 2.714 ; Rise ; SW[15] ;; SW[4] ; SW[15] ; -0.062 ; 0.505 ; Rise ; SW[15] ;; SW[5] ; SW[15] ; 0.786 ; 1.311 ; Rise ; SW[15] ;; SW[6] ; SW[15] ; 1.121 ; 1.690 ; Rise ; SW[15] ;; SW[7] ; SW[15] ; 0.382 ; 1.050 ; Rise ; SW[15] ;; SW[8] ; SW[15] ; 1.932 ; 2.525 ; Rise ; SW[15] ;; SW[9] ; SW[15] ; 2.523 ; 3.099 ; Rise ; SW[15] ;; SW[10] ; SW[15] ; 1.232 ; 1.916 ; Rise ; SW[15] ;; SW[11] ; SW[15] ; 2.740 ; 3.385 ; Rise ; SW[15] ;; SW[12] ; SW[15] ; 0.265 ; 0.903 ; Rise ; SW[15] ;; SW[13] ; SW[15] ; 0.900 ; 1.455 ; Rise ; SW[15] ;; SW[14] ; SW[15] ; 1.133 ; 1.667 ; Rise ; SW[15] ;; SW[15] ; SW[15] ; -1.252 ; -0.837 ; Rise ; SW[15] ;; KEY[*] ; clk_div:clkdiv_inst|clock_100Hz ; 5.645 ; 6.116 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; KEY[0] ; clk_div:clkdiv_inst|clock_100Hz ; 5.645 ; 6.116 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; KEY[1] ; clk_div:clkdiv_inst|clock_100Hz ; 5.323 ; 5.915 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; KEY[2] ; clk_div:clkdiv_inst|clock_100Hz ; 4.606 ; 5.157 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; KEY[3] ; clk_div:clkdiv_inst|clock_100Hz ; 5.384 ; 5.905 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[*] ; clk_div:clkdiv_inst|clock_100Hz ; 5.294 ; 5.955 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[0] ; clk_div:clkdiv_inst|clock_100Hz ; 5.294 ; 5.955 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[1] ; clk_div:clkdiv_inst|clock_100Hz ; 5.088 ; 5.703 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[2] ; clk_div:clkdiv_inst|clock_100Hz ; 4.138 ; 4.754 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[3] ; clk_div:clkdiv_inst|clock_100Hz ; 4.606 ; 5.249 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[4] ; clk_div:clkdiv_inst|clock_100Hz ; 4.198 ; 4.817 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[5] ; clk_div:clkdiv_inst|clock_100Hz ; 4.953 ; 5.611 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[6] ; clk_div:clkdiv_inst|clock_100Hz ; 4.157 ; 4.753 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[7] ; clk_div:clkdiv_inst|clock_100Hz ; 4.327 ; 4.880 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SW[*] ; clk_div:clkdiv_inst|clock_100Hz ; 6.248 ; 6.864 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SW[0] ; clk_div:clkdiv_inst|clock_100Hz ; 6.248 ; 6.864 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SW[1] ; clk_div:clkdiv_inst|clock_100Hz ; 5.198 ; 5.894 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SW[2] ; clk_div:clkdiv_inst|clock_100Hz ; 5.832 ; 6.422 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SW[3] ; clk_div:clkdiv_inst|clock_100Hz ; 5.577 ; 6.166 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SW[4] ; clk_div:clkdiv_inst|clock_100Hz ; 3.390 ; 3.957 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SW[5] ; clk_div:clkdiv_inst|clock_100Hz ; 4.238 ; 4.763 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SW[6] ; clk_div:clkdiv_inst|clock_100Hz ; 4.573 ; 5.142 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SW[7] ; clk_div:clkdiv_inst|clock_100Hz ; 3.834 ; 4.502 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SW[8] ; clk_div:clkdiv_inst|clock_100Hz ; 5.384 ; 5.977 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SW[9] ; clk_div:clkdiv_inst|clock_100Hz ; 5.975 ; 6.551 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SW[10] ; clk_div:clkdiv_inst|clock_100Hz ; 4.684 ; 5.368 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SW[11] ; clk_div:clkdiv_inst|clock_100Hz ; 6.192 ; 6.837 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SW[12] ; clk_div:clkdiv_inst|clock_100Hz ; 3.717 ; 4.355 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SW[13] ; clk_div:clkdiv_inst|clock_100Hz ; 4.352 ; 4.907 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SW[14] ; clk_div:clkdiv_inst|clock_100Hz ; 4.585 ; 5.119 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 2.200 ; 2.615 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; PS2_DAT ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 3.871 ; 4.335 ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ;; SW[*] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 4.560 ; 5.295 ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ;; SW[17] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 4.560 ; 5.295 ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ;+-------------+-------------------------------------------------------------+--------+--------+------------+-------------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Hold Times ;+-------------+-------------------------------------------------------------+--------+--------+------------+-------------------------------------------------------------+; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;+-------------+-------------------------------------------------------------+--------+--------+------------+-------------------------------------------------------------+; PS2_CLK ; CLOCK_50 ; -1.870 ; -2.369 ; Rise ; CLOCK_50 ;; SW[*] ; CLOCK_50 ; -2.494 ; -3.021 ; Rise ; CLOCK_50 ;; SW[14] ; CLOCK_50 ; -2.794 ; -3.379 ; Rise ; CLOCK_50 ;; SW[17] ; CLOCK_50 ; -2.494 ; -3.021 ; Rise ; CLOCK_50 ;; KEY[*] ; SW[15] ; 0.446 ; -0.079 ; Rise ; SW[15] ;; KEY[0] ; SW[15] ; -0.160 ; -0.621 ; Rise ; SW[15] ;; KEY[1] ; SW[15] ; -0.224 ; -0.773 ; Rise ; SW[15] ;; KEY[2] ; SW[15] ; 0.446 ; -0.079 ; Rise ; SW[15] ;; KEY[3] ; SW[15] ; -0.084 ; -0.568 ; Rise ; SW[15] ;; SRAM_DQ[*] ; SW[15] ; 0.970 ; 0.439 ; Rise ; SW[15] ;; SRAM_DQ[0] ; SW[15] ; 0.110 ; -0.520 ; Rise ; SW[15] ;; SRAM_DQ[1] ; SW[15] ; -0.002 ; -0.582 ; Rise ; SW[15] ;; SRAM_DQ[2] ; SW[15] ; 0.902 ; 0.322 ; Rise ; SW[15] ;; SRAM_DQ[3] ; SW[15] ; 0.553 ; -0.065 ; Rise ; SW[15] ;; SRAM_DQ[4] ; SW[15] ; 0.845 ; 0.241 ; Rise ; SW[15] ;; SRAM_DQ[5] ; SW[15] ; 0.367 ; -0.170 ; Rise ; SW[15] ;; SRAM_DQ[6] ; SW[15] ; 0.970 ; 0.354 ; Rise ; SW[15] ;; SRAM_DQ[7] ; SW[15] ; 0.954 ; 0.439 ; Rise ; SW[15] ;; SW[*] ; SW[15] ; 2.962 ; 2.569 ; Rise ; SW[15] ;; SW[0] ; SW[15] ; -0.760 ; -1.325 ; Rise ; SW[15] ;; SW[1] ; SW[15] ; -0.118 ; -0.770 ; Rise ; SW[15] ;; SW[2] ; SW[15] ; -0.668 ; -1.238 ; Rise ; SW[15] ;; SW[3] ; SW[15] ; -0.344 ; -0.903 ; Rise ; SW[15] ;; SW[4] ; SW[15] ; 1.558 ; 1.046 ; Rise ; SW[15] ;; SW[5] ; SW[15] ; 0.918 ; 0.425 ; Rise ; SW[15] ;; SW[6] ; SW[15] ; 0.571 ; 0.001 ; Rise ; SW[15] ;; SW[7] ; SW[15] ; 1.434 ; 0.800 ; Rise ; SW[15] ;; SW[8] ; SW[15] ; -0.022 ; -0.585 ; Rise ; SW[15] ;; SW[9] ; SW[15] ; -0.837 ; -1.392 ; Rise ; SW[15] ;; SW[10] ; SW[15] ; 0.369 ; -0.271 ; Rise ; SW[15] ;; SW[11] ; SW[15] ; -0.846 ; -1.467 ; Rise ; SW[15] ;; SW[12] ; SW[15] ; 1.249 ; 0.663 ; Rise ; SW[15] ;; SW[13] ; SW[15] ; 0.811 ; 0.289 ; Rise ; SW[15] ;; SW[14] ; SW[15] ; 0.520 ; -0.020 ; Rise ; SW[15] ;; SW[15] ; SW[15] ; 2.962 ; 2.569 ; Rise ; SW[15] ;; KEY[*] ; clk_div:clkdiv_inst|clock_100Hz ; -3.659 ; -4.184 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; KEY[0] ; clk_div:clkdiv_inst|clock_100Hz ; -4.265 ; -4.726 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; KEY[1] ; clk_div:clkdiv_inst|clock_100Hz ; -4.329 ; -4.878 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; KEY[2] ; clk_div:clkdiv_inst|clock_100Hz ; -3.659 ; -4.184 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; KEY[3] ; clk_div:clkdiv_inst|clock_100Hz ; -4.189 ; -4.673 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[*] ; clk_div:clkdiv_inst|clock_100Hz ; -3.135 ; -3.666 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[0] ; clk_div:clkdiv_inst|clock_100Hz ; -3.995 ; -4.625 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[1] ; clk_div:clkdiv_inst|clock_100Hz ; -4.107 ; -4.687 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[2] ; clk_div:clkdiv_inst|clock_100Hz ; -3.203 ; -3.783 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[3] ; clk_div:clkdiv_inst|clock_100Hz ; -3.552 ; -4.170 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[4] ; clk_div:clkdiv_inst|clock_100Hz ; -3.260 ; -3.864 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[5] ; clk_div:clkdiv_inst|clock_100Hz ; -3.738 ; -4.275 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[6] ; clk_div:clkdiv_inst|clock_100Hz ; -3.135 ; -3.751 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[7] ; clk_div:clkdiv_inst|clock_100Hz ; -3.151 ; -3.666 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SW[*] ; clk_div:clkdiv_inst|clock_100Hz ; -1.143 ; -1.536 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SW[0] ; clk_div:clkdiv_inst|clock_100Hz ; -4.865 ; -5.430 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SW[1] ; clk_div:clkdiv_inst|clock_100Hz ; -4.223 ; -4.875 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SW[2] ; clk_div:clkdiv_inst|clock_100Hz ; -4.773 ; -5.343 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SW[3] ; clk_div:clkdiv_inst|clock_100Hz ; -4.449 ; -5.008 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SW[4] ; clk_div:clkdiv_inst|clock_100Hz ; -2.547 ; -3.059 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SW[5] ; clk_div:clkdiv_inst|clock_100Hz ; -3.187 ; -3.680 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SW[6] ; clk_div:clkdiv_inst|clock_100Hz ; -3.534 ; -4.104 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SW[7] ; clk_div:clkdiv_inst|clock_100Hz ; -2.671 ; -3.305 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SW[8] ; clk_div:clkdiv_inst|clock_100Hz ; -4.127 ; -4.690 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SW[9] ; clk_div:clkdiv_inst|clock_100Hz ; -4.942 ; -5.497 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SW[10] ; clk_div:clkdiv_inst|clock_100Hz ; -3.736 ; -4.376 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SW[11] ; clk_div:clkdiv_inst|clock_100Hz ; -4.951 ; -5.572 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SW[12] ; clk_div:clkdiv_inst|clock_100Hz ; -2.856 ; -3.442 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SW[13] ; clk_div:clkdiv_inst|clock_100Hz ; -3.294 ; -3.816 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SW[14] ; clk_div:clkdiv_inst|clock_100Hz ; -3.585 ; -4.125 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; -1.143 ; -1.536 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; PS2_DAT ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; -1.298 ; -1.787 ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ;; SW[*] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; -2.404 ; -3.049 ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ;; SW[17] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; -2.404 ; -3.049 ; Rise ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ;+-------------+-------------------------------------------------------------+--------+--------+------------+-------------------------------------------------------------++-------------------------------------------------------------------------------------------------------------------+; Clock to Output Times ;+----------------+---------------------------------+--------+--------+------------+---------------------------------+; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;+----------------+---------------------------------+--------+--------+------------+---------------------------------+; LCD_DATA[*] ; CLOCK_50 ; 10.328 ; 10.123 ; Rise ; CLOCK_50 ;; LCD_DATA[0] ; CLOCK_50 ; 7.983 ; 7.880 ; Rise ; CLOCK_50 ;; LCD_DATA[1] ; CLOCK_50 ; 8.532 ; 8.378 ; Rise ; CLOCK_50 ;; LCD_DATA[2] ; CLOCK_50 ; 9.353 ; 9.246 ; Rise ; CLOCK_50 ;; LCD_DATA[3] ; CLOCK_50 ; 8.484 ; 8.484 ; Rise ; CLOCK_50 ;; LCD_DATA[4] ; CLOCK_50 ; 9.099 ; 9.156 ; Rise ; CLOCK_50 ;; LCD_DATA[5] ; CLOCK_50 ; 8.716 ; 8.745 ; Rise ; CLOCK_50 ;; LCD_DATA[6] ; CLOCK_50 ; 10.328 ; 10.123 ; Rise ; CLOCK_50 ;; LCD_DATA[7] ; CLOCK_50 ; 9.415 ; 9.270 ; Rise ; CLOCK_50 ;; LCD_EN ; CLOCK_50 ; 7.401 ; 7.465 ; Rise ; CLOCK_50 ;; LCD_ON ; CLOCK_50 ; 10.968 ; 10.828 ; Rise ; CLOCK_50 ;; LCD_RS ; CLOCK_50 ; 9.708 ; 9.634 ; Rise ; CLOCK_50 ;; HEX0[*] ; SW[15] ; 20.694 ; 20.735 ; Rise ; SW[15] ;; HEX0[0] ; SW[15] ; 18.632 ; 18.446 ; Rise ; SW[15] ;; HEX0[1] ; SW[15] ; 20.694 ; 20.735 ; Rise ; SW[15] ;; HEX0[2] ; SW[15] ; 18.808 ; 18.599 ; Rise ; SW[15] ;; HEX0[3] ; SW[15] ; 19.491 ; 19.029 ; Rise ; SW[15] ;; HEX0[4] ; SW[15] ; 16.396 ; 16.391 ; Rise ; SW[15] ;; HEX0[5] ; SW[15] ; 18.638 ; 18.347 ; Rise ; SW[15] ;; HEX0[6] ; SW[15] ; 17.191 ; 17.091 ; Rise ; SW[15] ;; HEX1[*] ; SW[15] ; 19.290 ; 19.595 ; Rise ; SW[15] ;; HEX1[0] ; SW[15] ; 16.583 ; 16.517 ; Rise ; SW[15] ;; HEX1[1] ; SW[15] ; 16.636 ; 16.485 ; Rise ; SW[15] ;; HEX1[2] ; SW[15] ; 17.760 ; 17.454 ; Rise ; SW[15] ;; HEX1[3] ; SW[15] ; 17.599 ; 17.233 ; Rise ; SW[15] ;; HEX1[4] ; SW[15] ; 16.230 ; 16.170 ; Rise ; SW[15] ;; HEX1[5] ; SW[15] ; 19.290 ; 18.800 ; Rise ; SW[15] ;; HEX1[6] ; SW[15] ; 18.950 ; 19.595 ; Rise ; SW[15] ;; HEX2[*] ; SW[15] ; 17.823 ; 17.849 ; Rise ; SW[15] ;; HEX2[0] ; SW[15] ; 17.199 ; 17.018 ; Rise ; SW[15] ;; HEX2[1] ; SW[15] ; 16.509 ; 16.412 ; Rise ; SW[15] ;; HEX2[2] ; SW[15] ; 17.096 ; 16.815 ; Rise ; SW[15] ;; HEX2[3] ; SW[15] ; 17.740 ; 17.473 ; Rise ; SW[15] ;; HEX2[4] ; SW[15] ; 15.869 ; 15.781 ; Rise ; SW[15] ;; HEX2[5] ; SW[15] ; 17.823 ; 17.441 ; Rise ; SW[15] ;; HEX2[6] ; SW[15] ; 17.491 ; 17.849 ; Rise ; SW[15] ;; HEX3[*] ; SW[15] ; 18.587 ; 18.488 ; Rise ; SW[15] ;; HEX3[0] ; SW[15] ; 17.620 ; 17.201 ; Rise ; SW[15] ;; HEX3[1] ; SW[15] ; 16.486 ; 16.419 ; Rise ; SW[15] ;; HEX3[2] ; SW[15] ; 18.522 ; 18.128 ; Rise ; SW[15] ;; HEX3[3] ; SW[15] ; 16.595 ; 16.580 ; Rise ; SW[15] ;; HEX3[4] ; SW[15] ; 18.587 ; 18.488 ; Rise ; SW[15] ;; HEX3[5] ; SW[15] ; 17.148 ; 17.110 ; Rise ; SW[15] ;; HEX3[6] ; SW[15] ; 17.509 ; 17.586 ; Rise ; SW[15] ;; HEX4[*] ; SW[15] ; 17.409 ; 17.183 ; Rise ; SW[15] ;; HEX4[0] ; SW[15] ; 16.409 ; 16.350 ; Rise ; SW[15] ;; HEX4[1] ; SW[15] ; 16.217 ; 16.196 ; Rise ; SW[15] ;; HEX4[2] ; SW[15] ; 16.005 ; 16.011 ; Rise ; SW[15] ;; HEX4[3] ; SW[15] ; 17.409 ; 17.166 ; Rise ; SW[15] ;; HEX4[4] ; SW[15] ; 16.351 ; 16.213 ; Rise ; SW[15] ;; HEX4[5] ; SW[15] ; 17.307 ; 17.183 ; Rise ; SW[15] ;; HEX4[6] ; SW[15] ; 15.414 ; 15.421 ; Rise ; SW[15] ;; HEX5[*] ; SW[15] ; 18.588 ; 18.222 ; Rise ; SW[15] ;; HEX5[0] ; SW[15] ; 16.615 ; 16.404 ; Rise ; SW[15] ;; HEX5[1] ; SW[15] ; 18.588 ; 18.222 ; Rise ; SW[15] ;; HEX5[2] ; SW[15] ; 18.050 ; 17.857 ; Rise ; SW[15] ;; HEX5[3] ; SW[15] ; 16.392 ; 16.298 ; Rise ; SW[15] ;; HEX5[4] ; SW[15] ; 16.916 ; 16.684 ; Rise ; SW[15] ;; HEX5[5] ; SW[15] ; 16.650 ; 16.409 ; Rise ; SW[15] ;; HEX5[6] ; SW[15] ; 16.541 ; 16.586 ; Rise ; SW[15] ;; HEX6[*] ; SW[15] ; 17.065 ; 16.615 ; Rise ; SW[15] ;; HEX6[0] ; SW[15] ; 16.244 ; 16.020 ; Rise ; SW[15] ;; HEX6[1] ; SW[15] ; 14.686 ; 14.649 ; Rise ; SW[15] ;; HEX6[2] ; SW[15] ; 14.789 ; 14.611 ; Rise ; SW[15] ;; HEX6[3] ; SW[15] ; 15.916 ; 15.736 ; Rise ; SW[15] ;; HEX6[4] ; SW[15] ; 14.959 ; 14.808 ; Rise ; SW[15] ;; HEX6[5] ; SW[15] ; 17.065 ; 16.615 ; Rise ; SW[15] ;; HEX6[6] ; SW[15] ; 15.067 ; 15.157 ; Rise ; SW[15] ;; HEX7[*] ; SW[15] ; 15.350 ; 15.101 ; Rise ; SW[15] ;; HEX7[0] ; SW[15] ; 15.350 ; 15.101 ; Rise ; SW[15] ;; HEX7[1] ; SW[15] ; 14.804 ; 14.671 ; Rise ; SW[15] ;; HEX7[2] ; SW[15] ; 14.361 ; 14.194 ; Rise ; SW[15] ;; HEX7[3] ; SW[15] ; 14.395 ; 14.233 ; Rise ; SW[15] ;; HEX7[4] ; SW[15] ; 14.876 ; 14.739 ; Rise ; SW[15] ;; HEX7[5] ; SW[15] ; 14.919 ; 14.707 ; Rise ; SW[15] ;; HEX7[6] ; SW[15] ; 14.667 ; 14.850 ; Rise ; SW[15] ;; LEDG[*] ; SW[15] ; 17.685 ; 17.552 ; Rise ; SW[15] ;; LEDG[0] ; SW[15] ; 16.046 ; 16.156 ; Rise ; SW[15] ;; LEDG[1] ; SW[15] ; 16.128 ; 16.251 ; Rise ; SW[15] ;; LEDG[2] ; SW[15] ; 16.148 ; 16.267 ; Rise ; SW[15] ;; LEDG[3] ; SW[15] ; 16.894 ; 16.944 ; Rise ; SW[15] ;; LEDG[4] ; SW[15] ; 15.635 ; 15.788 ; Rise ; SW[15] ;; LEDG[5] ; SW[15] ; 16.102 ; 16.206 ; Rise ; SW[15] ;; LEDG[6] ; SW[15] ; 17.685 ; 17.552 ; Rise ; SW[15] ;; LEDG[7] ; SW[15] ; 16.877 ; 16.803 ; Rise ; SW[15] ;; LEDR[*] ; SW[15] ; 19.029 ; 19.041 ; Rise ; SW[15] ;; LEDR[0] ; SW[15] ; 17.286 ; 17.165 ; Rise ; SW[15] ;; LEDR[1] ; SW[15] ; 15.773 ; 15.896 ; Rise ; SW[15] ;; LEDR[2] ; SW[15] ; 17.424 ; 17.325 ; Rise ; SW[15] ;; LEDR[3] ; SW[15] ; 17.350 ; 17.369 ; Rise ; SW[15] ;; LEDR[4] ; SW[15] ; 16.061 ; 16.114 ; Rise ; SW[15] ;; LEDR[5] ; SW[15] ; 15.924 ; 15.967 ; Rise ; SW[15] ;; LEDR[6] ; SW[15] ; 16.137 ; 16.146 ; Rise ; SW[15] ;; LEDR[7] ; SW[15] ; 15.817 ; 15.843 ; Rise ; SW[15] ;; LEDR[8] ; SW[15] ; 17.857 ; 17.698 ; Rise ; SW[15] ;; LEDR[9] ; SW[15] ; 17.913 ; 18.061 ; Rise ; SW[15] ;; LEDR[10] ; SW[15] ; 17.252 ; 17.119 ; Rise ; SW[15] ;; LEDR[11] ; SW[15] ; 15.848 ; 15.940 ; Rise ; SW[15] ;; LEDR[12] ; SW[15] ; 15.357 ; 15.435 ; Rise ; SW[15] ;; LEDR[13] ; SW[15] ; 15.735 ; 15.764 ; Rise ; SW[15] ;; LEDR[14] ; SW[15] ; 17.348 ; 17.214 ; Rise ; SW[15] ;; LEDR[15] ; SW[15] ; 19.029 ; 19.041 ; Rise ; SW[15] ;; SRAM_ADDR[*] ; SW[15] ; 19.577 ; 19.569 ; Rise ; SW[15] ;; SRAM_ADDR[0] ; SW[15] ; 12.822 ; 12.869 ; Rise ; SW[15] ;; SRAM_ADDR[1] ; SW[15] ; 13.849 ; 13.940 ; Rise ; SW[15] ;; SRAM_ADDR[2] ; SW[15] ; 13.122 ; 13.206 ; Rise ; SW[15] ;; SRAM_ADDR[3] ; SW[15] ; 12.818 ; 12.873 ; Rise ; SW[15] ;; SRAM_ADDR[4] ; SW[15] ; 13.732 ; 13.854 ; Rise ; SW[15] ;; SRAM_ADDR[5] ; SW[15] ; 19.258 ; 19.073 ; Rise ; SW[15] ;; SRAM_ADDR[6] ; SW[15] ; 13.293 ; 13.312 ; Rise ; SW[15] ;; SRAM_ADDR[7] ; SW[15] ; 13.388 ; 13.424 ; Rise ; SW[15] ;; SRAM_ADDR[8] ; SW[15] ; 19.212 ; 19.153 ; Rise ; SW[15] ;; SRAM_ADDR[9] ; SW[15] ; 15.378 ; 15.091 ; Rise ; SW[15] ;; SRAM_ADDR[10] ; SW[15] ; 19.114 ; 19.124 ; Rise ; SW[15] ;; SRAM_ADDR[11] ; SW[15] ; 19.577 ; 19.547 ; Rise ; SW[15] ;; SRAM_ADDR[12] ; SW[15] ; 18.397 ; 18.075 ; Rise ; SW[15] ;; SRAM_ADDR[13] ; SW[15] ; 19.570 ; 19.569 ; Rise ; SW[15] ;; SRAM_ADDR[14] ; SW[15] ; 14.106 ; 14.028 ; Rise ; SW[15] ;; SRAM_ADDR[15] ; SW[15] ; 17.621 ; 18.177 ; Rise ; SW[15] ;; SRAM_DQ[*] ; SW[15] ; 18.759 ; 18.689 ; Rise ; SW[15] ;; SRAM_DQ[0] ; SW[15] ; 18.027 ; 17.975 ; Rise ; SW[15] ;; SRAM_DQ[1] ; SW[15] ; 17.692 ; 17.628 ; Rise ; SW[15] ;; SRAM_DQ[2] ; SW[15] ; 18.759 ; 18.689 ; Rise ; SW[15] ;; SRAM_DQ[3] ; SW[15] ; 17.063 ; 17.063 ; Rise ; SW[15] ;; SRAM_DQ[4] ; SW[15] ; 17.938 ; 17.959 ; Rise ; SW[15] ;; SRAM_DQ[5] ; SW[15] ; 16.165 ; 16.239 ; Rise ; SW[15] ;; SRAM_DQ[6] ; SW[15] ; 18.420 ; 18.496 ; Rise ; SW[15] ;; SRAM_DQ[7] ; SW[15] ; 17.168 ; 17.137 ; Rise ; SW[15] ;; SRAM_OE_N ; SW[15] ; 21.939 ; 21.616 ; Rise ; SW[15] ;; SRAM_WE_N ; SW[15] ; 15.678 ; 15.826 ; Rise ; SW[15] ;; SRAM_OE_N ; T80se:z80_inst|MREQ_n ; ; 11.836 ; Rise ; T80se:z80_inst|MREQ_n ;; SRAM_WE_N ; T80se:z80_inst|MREQ_n ; ; 9.592 ; Rise ; T80se:z80_inst|MREQ_n ;; SRAM_OE_N ; T80se:z80_inst|MREQ_n ; 12.124 ; ; Fall ; T80se:z80_inst|MREQ_n ;; SRAM_WE_N ; T80se:z80_inst|MREQ_n ; 9.401 ; ; Fall ; T80se:z80_inst|MREQ_n ;; HEX0[*] ; clk_div:clkdiv_inst|clock_100Hz ; 16.589 ; 16.630 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX0[0] ; clk_div:clkdiv_inst|clock_100Hz ; 14.527 ; 14.341 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX0[1] ; clk_div:clkdiv_inst|clock_100Hz ; 16.589 ; 16.630 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX0[2] ; clk_div:clkdiv_inst|clock_100Hz ; 14.703 ; 14.494 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX0[3] ; clk_div:clkdiv_inst|clock_100Hz ; 15.386 ; 14.924 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX0[4] ; clk_div:clkdiv_inst|clock_100Hz ; 12.291 ; 12.286 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX0[5] ; clk_div:clkdiv_inst|clock_100Hz ; 14.533 ; 14.242 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX0[6] ; clk_div:clkdiv_inst|clock_100Hz ; 13.086 ; 12.986 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX1[*] ; clk_div:clkdiv_inst|clock_100Hz ; 15.185 ; 15.490 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX1[0] ; clk_div:clkdiv_inst|clock_100Hz ; 12.478 ; 12.412 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX1[1] ; clk_div:clkdiv_inst|clock_100Hz ; 12.531 ; 12.380 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX1[2] ; clk_div:clkdiv_inst|clock_100Hz ; 13.655 ; 13.349 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX1[3] ; clk_div:clkdiv_inst|clock_100Hz ; 13.494 ; 13.128 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX1[4] ; clk_div:clkdiv_inst|clock_100Hz ; 12.125 ; 12.065 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX1[5] ; clk_div:clkdiv_inst|clock_100Hz ; 15.185 ; 14.695 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX1[6] ; clk_div:clkdiv_inst|clock_100Hz ; 14.845 ; 15.490 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX2[*] ; clk_div:clkdiv_inst|clock_100Hz ; 13.718 ; 13.744 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX2[0] ; clk_div:clkdiv_inst|clock_100Hz ; 13.094 ; 12.913 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX2[1] ; clk_div:clkdiv_inst|clock_100Hz ; 12.404 ; 12.307 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX2[2] ; clk_div:clkdiv_inst|clock_100Hz ; 12.991 ; 12.710 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX2[3] ; clk_div:clkdiv_inst|clock_100Hz ; 13.635 ; 13.368 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX2[4] ; clk_div:clkdiv_inst|clock_100Hz ; 11.764 ; 11.676 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX2[5] ; clk_div:clkdiv_inst|clock_100Hz ; 13.718 ; 13.336 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX2[6] ; clk_div:clkdiv_inst|clock_100Hz ; 13.386 ; 13.744 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX3[*] ; clk_div:clkdiv_inst|clock_100Hz ; 14.482 ; 14.383 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX3[0] ; clk_div:clkdiv_inst|clock_100Hz ; 13.515 ; 13.096 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX3[1] ; clk_div:clkdiv_inst|clock_100Hz ; 12.381 ; 12.314 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX3[2] ; clk_div:clkdiv_inst|clock_100Hz ; 14.417 ; 14.023 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX3[3] ; clk_div:clkdiv_inst|clock_100Hz ; 12.490 ; 12.475 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX3[4] ; clk_div:clkdiv_inst|clock_100Hz ; 14.482 ; 14.383 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX3[5] ; clk_div:clkdiv_inst|clock_100Hz ; 13.043 ; 13.005 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX3[6] ; clk_div:clkdiv_inst|clock_100Hz ; 13.404 ; 13.481 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX4[*] ; clk_div:clkdiv_inst|clock_100Hz ; 13.304 ; 13.078 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX4[0] ; clk_div:clkdiv_inst|clock_100Hz ; 12.304 ; 12.245 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX4[1] ; clk_div:clkdiv_inst|clock_100Hz ; 12.112 ; 12.091 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX4[2] ; clk_div:clkdiv_inst|clock_100Hz ; 11.900 ; 11.906 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX4[3] ; clk_div:clkdiv_inst|clock_100Hz ; 13.304 ; 13.061 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX4[4] ; clk_div:clkdiv_inst|clock_100Hz ; 12.246 ; 12.108 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX4[5] ; clk_div:clkdiv_inst|clock_100Hz ; 13.202 ; 13.078 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX4[6] ; clk_div:clkdiv_inst|clock_100Hz ; 11.309 ; 11.316 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX5[*] ; clk_div:clkdiv_inst|clock_100Hz ; 14.483 ; 14.117 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX5[0] ; clk_div:clkdiv_inst|clock_100Hz ; 12.510 ; 12.299 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX5[1] ; clk_div:clkdiv_inst|clock_100Hz ; 14.483 ; 14.117 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX5[2] ; clk_div:clkdiv_inst|clock_100Hz ; 13.945 ; 13.752 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX5[3] ; clk_div:clkdiv_inst|clock_100Hz ; 12.287 ; 12.193 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX5[4] ; clk_div:clkdiv_inst|clock_100Hz ; 12.811 ; 12.579 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX5[5] ; clk_div:clkdiv_inst|clock_100Hz ; 12.545 ; 12.304 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX5[6] ; clk_div:clkdiv_inst|clock_100Hz ; 12.436 ; 12.481 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX6[*] ; clk_div:clkdiv_inst|clock_100Hz ; 12.960 ; 12.510 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX6[0] ; clk_div:clkdiv_inst|clock_100Hz ; 12.139 ; 11.915 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX6[1] ; clk_div:clkdiv_inst|clock_100Hz ; 10.581 ; 10.544 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX6[2] ; clk_div:clkdiv_inst|clock_100Hz ; 10.684 ; 10.506 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX6[3] ; clk_div:clkdiv_inst|clock_100Hz ; 11.811 ; 11.631 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX6[4] ; clk_div:clkdiv_inst|clock_100Hz ; 10.854 ; 10.703 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX6[5] ; clk_div:clkdiv_inst|clock_100Hz ; 12.960 ; 12.510 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX6[6] ; clk_div:clkdiv_inst|clock_100Hz ; 10.962 ; 11.052 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX7[*] ; clk_div:clkdiv_inst|clock_100Hz ; 11.245 ; 10.996 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX7[0] ; clk_div:clkdiv_inst|clock_100Hz ; 11.245 ; 10.996 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX7[1] ; clk_div:clkdiv_inst|clock_100Hz ; 10.699 ; 10.566 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX7[2] ; clk_div:clkdiv_inst|clock_100Hz ; 10.256 ; 10.089 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX7[3] ; clk_div:clkdiv_inst|clock_100Hz ; 10.290 ; 10.128 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX7[4] ; clk_div:clkdiv_inst|clock_100Hz ; 10.771 ; 10.634 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX7[5] ; clk_div:clkdiv_inst|clock_100Hz ; 10.814 ; 10.602 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX7[6] ; clk_div:clkdiv_inst|clock_100Hz ; 10.562 ; 10.745 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDG[*] ; clk_div:clkdiv_inst|clock_100Hz ; 13.580 ; 13.447 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDG[0] ; clk_div:clkdiv_inst|clock_100Hz ; 11.941 ; 12.051 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDG[1] ; clk_div:clkdiv_inst|clock_100Hz ; 12.023 ; 12.146 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDG[2] ; clk_div:clkdiv_inst|clock_100Hz ; 12.043 ; 12.162 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDG[3] ; clk_div:clkdiv_inst|clock_100Hz ; 12.789 ; 12.839 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDG[4] ; clk_div:clkdiv_inst|clock_100Hz ; 11.530 ; 11.683 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDG[5] ; clk_div:clkdiv_inst|clock_100Hz ; 11.997 ; 12.101 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDG[6] ; clk_div:clkdiv_inst|clock_100Hz ; 13.580 ; 13.447 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDG[7] ; clk_div:clkdiv_inst|clock_100Hz ; 12.772 ; 12.698 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDR[*] ; clk_div:clkdiv_inst|clock_100Hz ; 14.924 ; 14.936 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDR[0] ; clk_div:clkdiv_inst|clock_100Hz ; 13.181 ; 13.060 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDR[1] ; clk_div:clkdiv_inst|clock_100Hz ; 11.668 ; 11.791 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDR[2] ; clk_div:clkdiv_inst|clock_100Hz ; 13.319 ; 13.220 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDR[3] ; clk_div:clkdiv_inst|clock_100Hz ; 13.245 ; 13.264 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDR[4] ; clk_div:clkdiv_inst|clock_100Hz ; 11.956 ; 12.009 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDR[5] ; clk_div:clkdiv_inst|clock_100Hz ; 11.819 ; 11.862 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDR[6] ; clk_div:clkdiv_inst|clock_100Hz ; 12.032 ; 12.041 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDR[7] ; clk_div:clkdiv_inst|clock_100Hz ; 11.712 ; 11.738 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDR[8] ; clk_div:clkdiv_inst|clock_100Hz ; 13.752 ; 13.593 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDR[9] ; clk_div:clkdiv_inst|clock_100Hz ; 13.808 ; 13.956 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDR[10] ; clk_div:clkdiv_inst|clock_100Hz ; 13.147 ; 13.014 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDR[11] ; clk_div:clkdiv_inst|clock_100Hz ; 11.743 ; 11.835 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDR[12] ; clk_div:clkdiv_inst|clock_100Hz ; 11.252 ; 11.330 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDR[13] ; clk_div:clkdiv_inst|clock_100Hz ; 11.630 ; 11.659 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDR[14] ; clk_div:clkdiv_inst|clock_100Hz ; 13.243 ; 13.109 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDR[15] ; clk_div:clkdiv_inst|clock_100Hz ; 14.924 ; 14.936 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_ADDR[*] ; clk_div:clkdiv_inst|clock_100Hz ; 15.472 ; 15.464 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_ADDR[0] ; clk_div:clkdiv_inst|clock_100Hz ; 8.717 ; 8.764 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_ADDR[1] ; clk_div:clkdiv_inst|clock_100Hz ; 9.744 ; 9.835 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_ADDR[2] ; clk_div:clkdiv_inst|clock_100Hz ; 9.017 ; 9.101 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_ADDR[3] ; clk_div:clkdiv_inst|clock_100Hz ; 8.713 ; 8.768 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_ADDR[4] ; clk_div:clkdiv_inst|clock_100Hz ; 9.627 ; 9.749 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_ADDR[5] ; clk_div:clkdiv_inst|clock_100Hz ; 15.153 ; 14.968 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_ADDR[6] ; clk_div:clkdiv_inst|clock_100Hz ; 9.188 ; 9.207 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_ADDR[7] ; clk_div:clkdiv_inst|clock_100Hz ; 9.283 ; 9.319 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_ADDR[8] ; clk_div:clkdiv_inst|clock_100Hz ; 15.107 ; 15.048 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_ADDR[9] ; clk_div:clkdiv_inst|clock_100Hz ; 11.273 ; 10.986 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_ADDR[10] ; clk_div:clkdiv_inst|clock_100Hz ; 15.009 ; 15.019 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_ADDR[11] ; clk_div:clkdiv_inst|clock_100Hz ; 15.472 ; 15.442 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_ADDR[12] ; clk_div:clkdiv_inst|clock_100Hz ; 14.292 ; 13.970 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_ADDR[13] ; clk_div:clkdiv_inst|clock_100Hz ; 15.465 ; 15.464 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_ADDR[14] ; clk_div:clkdiv_inst|clock_100Hz ; 10.001 ; 9.923 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_ADDR[15] ; clk_div:clkdiv_inst|clock_100Hz ; 13.516 ; 14.072 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[*] ; clk_div:clkdiv_inst|clock_100Hz ; 14.654 ; 14.584 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[0] ; clk_div:clkdiv_inst|clock_100Hz ; 13.922 ; 13.870 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[1] ; clk_div:clkdiv_inst|clock_100Hz ; 13.587 ; 13.523 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[2] ; clk_div:clkdiv_inst|clock_100Hz ; 14.654 ; 14.584 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[3] ; clk_div:clkdiv_inst|clock_100Hz ; 12.958 ; 12.958 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[4] ; clk_div:clkdiv_inst|clock_100Hz ; 13.833 ; 13.854 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[5] ; clk_div:clkdiv_inst|clock_100Hz ; 12.060 ; 12.134 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[6] ; clk_div:clkdiv_inst|clock_100Hz ; 14.315 ; 14.391 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[7] ; clk_div:clkdiv_inst|clock_100Hz ; 13.063 ; 13.032 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_OE_N ; clk_div:clkdiv_inst|clock_100Hz ; 17.834 ; 17.511 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_WE_N ; clk_div:clkdiv_inst|clock_100Hz ; 11.573 ; 11.721 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; VGA_B[*] ; clk_div:clkdiv_inst|clock_25MHz ; 11.784 ; 11.612 ; Rise ; clk_div:clkdiv_inst|clock_25MHz ;; VGA_B[4] ; clk_div:clkdiv_inst|clock_25MHz ; 11.784 ; 11.612 ; Rise ; clk_div:clkdiv_inst|clock_25MHz ;; VGA_B[5] ; clk_div:clkdiv_inst|clock_25MHz ; 11.318 ; 11.182 ; Rise ; clk_div:clkdiv_inst|clock_25MHz ;; VGA_B[6] ; clk_div:clkdiv_inst|clock_25MHz ; 10.691 ; 10.728 ; Rise ; clk_div:clkdiv_inst|clock_25MHz ;; VGA_B[7] ; clk_div:clkdiv_inst|clock_25MHz ; 11.566 ; 11.409 ; Rise ; clk_div:clkdiv_inst|clock_25MHz ;; VGA_CLK ; clk_div:clkdiv_inst|clock_25MHz ; 4.903 ; ; Rise ; clk_div:clkdiv_inst|clock_25MHz ;; VGA_HS ; clk_div:clkdiv_inst|clock_25MHz ; 9.656 ; 9.627 ; Rise ; clk_div:clkdiv_inst|clock_25MHz ;; VGA_VS ; clk_div:clkdiv_inst|clock_25MHz ; 11.726 ; 11.551 ; Rise ; clk_div:clkdiv_inst|clock_25MHz ;; VGA_CLK ; clk_div:clkdiv_inst|clock_25MHz ; ; 4.874 ; Fall ; clk_div:clkdiv_inst|clock_25MHz ;+----------------+---------------------------------+--------+--------+------------+---------------------------------++-------------------------------------------------------------------------------------------------------------------+; Minimum Clock to Output Times ;+----------------+---------------------------------+--------+--------+------------+---------------------------------+; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;+----------------+---------------------------------+--------+--------+------------+---------------------------------+; LCD_DATA[*] ; CLOCK_50 ; 7.705 ; 7.602 ; Rise ; CLOCK_50 ;; LCD_DATA[0] ; CLOCK_50 ; 7.705 ; 7.602 ; Rise ; CLOCK_50 ;; LCD_DATA[1] ; CLOCK_50 ; 8.233 ; 8.081 ; Rise ; CLOCK_50 ;; LCD_DATA[2] ; CLOCK_50 ; 9.022 ; 8.915 ; Rise ; CLOCK_50 ;; LCD_DATA[3] ; CLOCK_50 ; 8.182 ; 8.186 ; Rise ; CLOCK_50 ;; LCD_DATA[4] ; CLOCK_50 ; 8.773 ; 8.832 ; Rise ; CLOCK_50 ;; LCD_DATA[5] ; CLOCK_50 ; 8.404 ; 8.436 ; Rise ; CLOCK_50 ;; LCD_DATA[6] ; CLOCK_50 ; 9.958 ; 9.757 ; Rise ; CLOCK_50 ;; LCD_DATA[7] ; CLOCK_50 ; 9.083 ; 8.940 ; Rise ; CLOCK_50 ;; LCD_EN ; CLOCK_50 ; 7.144 ; 7.209 ; Rise ; CLOCK_50 ;; LCD_ON ; CLOCK_50 ; 10.571 ; 10.432 ; Rise ; CLOCK_50 ;; LCD_RS ; CLOCK_50 ; 9.362 ; 9.287 ; Rise ; CLOCK_50 ;; HEX0[*] ; SW[15] ; 14.800 ; 14.807 ; Rise ; SW[15] ;; HEX0[0] ; SW[15] ; 16.997 ; 16.829 ; Rise ; SW[15] ;; HEX0[1] ; SW[15] ; 19.075 ; 19.157 ; Rise ; SW[15] ;; HEX0[2] ; SW[15] ; 17.166 ; 16.976 ; Rise ; SW[15] ;; HEX0[3] ; SW[15] ; 17.751 ; 17.336 ; Rise ; SW[15] ;; HEX0[4] ; SW[15] ; 14.800 ; 14.807 ; Rise ; SW[15] ;; HEX0[5] ; SW[15] ; 17.025 ; 16.743 ; Rise ; SW[15] ;; HEX0[6] ; SW[15] ; 15.536 ; 15.490 ; Rise ; SW[15] ;; HEX1[*] ; SW[15] ; 14.533 ; 14.463 ; Rise ; SW[15] ;; HEX1[0] ; SW[15] ; 14.910 ; 14.819 ; Rise ; SW[15] ;; HEX1[1] ; SW[15] ; 15.007 ; 14.859 ; Rise ; SW[15] ;; HEX1[2] ; SW[15] ; 16.101 ; 15.722 ; Rise ; SW[15] ;; HEX1[3] ; SW[15] ; 15.795 ; 15.456 ; Rise ; SW[15] ;; HEX1[4] ; SW[15] ; 14.533 ; 14.463 ; Rise ; SW[15] ;; HEX1[5] ; SW[15] ; 17.543 ; 17.017 ; Rise ; SW[15] ;; HEX1[6] ; SW[15] ; 17.169 ; 17.809 ; Rise ; SW[15] ;; HEX2[*] ; SW[15] ; 13.926 ; 13.887 ; Rise ; SW[15] ;; HEX2[0] ; SW[15] ; 15.767 ; 15.657 ; Rise ; SW[15] ;; HEX2[1] ; SW[15] ; 15.124 ; 15.068 ; Rise ; SW[15] ;; HEX2[2] ; SW[15] ; 15.669 ; 15.454 ; Rise ; SW[15] ;; HEX2[3] ; SW[15] ; 15.782 ; 15.437 ; Rise ; SW[15] ;; HEX2[4] ; SW[15] ; 13.926 ; 13.887 ; Rise ; SW[15] ;; HEX2[5] ; SW[15] ; 15.786 ; 15.431 ; Rise ; SW[15] ;; HEX2[6] ; SW[15] ; 15.835 ; 16.226 ; Rise ; SW[15] ;; HEX3[*] ; SW[15] ; 14.858 ; 14.756 ; Rise ; SW[15] ;; HEX3[0] ; SW[15] ; 16.148 ; 15.756 ; Rise ; SW[15] ;; HEX3[1] ; SW[15] ; 15.069 ; 14.978 ; Rise ; SW[15] ;; HEX3[2] ; SW[15] ; 17.141 ; 16.867 ; Rise ; SW[15] ;; HEX3[3] ; SW[15] ; 14.858 ; 14.756 ; Rise ; SW[15] ;; HEX3[4] ; SW[15] ; 16.952 ; 16.820 ; Rise ; SW[15] ;; HEX3[5] ; SW[15] ; 15.564 ; 15.484 ; Rise ; SW[15] ;; HEX3[6] ; SW[15] ; 15.851 ; 15.976 ; Rise ; SW[15] ;; HEX4[*] ; SW[15] ; 13.832 ; 13.886 ; Rise ; SW[15] ;; HEX4[0] ; SW[15] ; 14.693 ; 14.597 ; Rise ; SW[15] ;; HEX4[1] ; SW[15] ; 14.510 ; 14.449 ; Rise ; SW[15] ;; HEX4[2] ; SW[15] ; 14.310 ; 14.346 ; Rise ; SW[15] ;; HEX4[3] ; SW[15] ; 15.650 ; 15.408 ; Rise ; SW[15] ;; HEX4[4] ; SW[15] ; 14.781 ; 14.647 ; Rise ; SW[15] ;; HEX4[5] ; SW[15] ; 15.680 ; 15.551 ; Rise ; SW[15] ;; HEX4[6] ; SW[15] ; 13.832 ; 13.886 ; Rise ; SW[15] ;; HEX5[*] ; SW[15] ; 14.756 ; 14.578 ; Rise ; SW[15] ;; HEX5[0] ; SW[15] ; 15.061 ; 14.865 ; Rise ; SW[15] ;; HEX5[1] ; SW[15] ; 17.077 ; 16.742 ; Rise ; SW[15] ;; HEX5[2] ; SW[15] ; 16.429 ; 16.257 ; Rise ; SW[15] ;; HEX5[3] ; SW[15] ; 14.756 ; 14.578 ; Rise ; SW[15] ;; HEX5[4] ; SW[15] ; 15.317 ; 15.089 ; Rise ; SW[15] ;; HEX5[5] ; SW[15] ; 14.919 ; 14.731 ; Rise ; SW[15] ;; HEX5[6] ; SW[15] ; 14.922 ; 15.014 ; Rise ; SW[15] ;; HEX6[*] ; SW[15] ; 13.175 ; 12.996 ; Rise ; SW[15] ;; HEX6[0] ; SW[15] ; 14.609 ; 14.326 ; Rise ; SW[15] ;; HEX6[1] ; SW[15] ; 13.175 ; 13.011 ; Rise ; SW[15] ;; HEX6[2] ; SW[15] ; 13.237 ; 12.996 ; Rise ; SW[15] ;; HEX6[3] ; SW[15] ; 14.205 ; 14.025 ; Rise ; SW[15] ;; HEX6[4] ; SW[15] ; 13.320 ; 13.161 ; Rise ; SW[15] ;; HEX6[5] ; SW[15] ; 15.436 ; 14.947 ; Rise ; SW[15] ;; HEX6[6] ; SW[15] ; 13.378 ; 13.492 ; Rise ; SW[15] ;; HEX7[*] ; SW[15] ; 12.890 ; 12.740 ; Rise ; SW[15] ;; HEX7[0] ; SW[15] ; 13.778 ; 13.551 ; Rise ; SW[15] ;; HEX7[1] ; SW[15] ; 13.304 ; 13.125 ; Rise ; SW[15] ;; HEX7[2] ; SW[15] ; 12.890 ; 12.740 ; Rise ; SW[15] ;; HEX7[3] ; SW[15] ; 12.923 ; 12.776 ; Rise ; SW[15] ;; HEX7[4] ; SW[15] ; 13.509 ; 13.242 ; Rise ; SW[15] ;; HEX7[5] ; SW[15] ; 13.374 ; 13.188 ; Rise ; SW[15] ;; HEX7[6] ; SW[15] ; 13.137 ; 13.304 ; Rise ; SW[15] ;; LEDG[*] ; SW[15] ; 14.526 ; 14.671 ; Rise ; SW[15] ;; LEDG[0] ; SW[15] ; 14.919 ; 15.023 ; Rise ; SW[15] ;; LEDG[1] ; SW[15] ; 14.998 ; 15.114 ; Rise ; SW[15] ;; LEDG[2] ; SW[15] ; 15.019 ; 15.132 ; Rise ; SW[15] ;; LEDG[3] ; SW[15] ; 15.736 ; 15.783 ; Rise ; SW[15] ;; LEDG[4] ; SW[15] ; 14.526 ; 14.671 ; Rise ; SW[15] ;; LEDG[5] ; SW[15] ; 14.975 ; 15.073 ; Rise ; SW[15] ;; LEDG[6] ; SW[15] ; 16.494 ; 16.364 ; Rise ; SW[15] ;; LEDG[7] ; SW[15] ; 15.720 ; 15.646 ; Rise ; SW[15] ;; LEDR[*] ; SW[15] ; 14.259 ; 14.332 ; Rise ; SW[15] ;; LEDR[0] ; SW[15] ; 16.111 ; 15.994 ; Rise ; SW[15] ;; LEDR[1] ; SW[15] ; 14.656 ; 14.773 ; Rise ; SW[15] ;; LEDR[2] ; SW[15] ; 16.241 ; 16.144 ; Rise ; SW[15] ;; LEDR[3] ; SW[15] ; 16.171 ; 16.187 ; Rise ; SW[15] ;; LEDR[4] ; SW[15] ; 14.933 ; 14.983 ; Rise ; SW[15] ;; LEDR[5] ; SW[15] ; 14.802 ; 14.841 ; Rise ; SW[15] ;; LEDR[6] ; SW[15] ; 15.007 ; 15.014 ; Rise ; SW[15] ;; LEDR[7] ; SW[15] ; 14.699 ; 14.723 ; Rise ; SW[15] ;; LEDR[8] ; SW[15] ; 16.657 ; 16.502 ; Rise ; SW[15] ;; LEDR[9] ; SW[15] ; 16.765 ; 16.910 ; Rise ; SW[15] ;; LEDR[10] ; SW[15] ; 16.076 ; 15.947 ; Rise ; SW[15] ;; LEDR[11] ; SW[15] ; 14.729 ; 14.816 ; Rise ; SW[15] ;; LEDR[12] ; SW[15] ; 14.259 ; 14.332 ; Rise ; SW[15] ;; LEDR[13] ; SW[15] ; 14.620 ; 14.646 ; Rise ; SW[15] ;; LEDR[14] ; SW[15] ; 16.169 ; 16.039 ; Rise ; SW[15] ;; LEDR[15] ; SW[15] ; 17.837 ; 17.851 ; Rise ; SW[15] ;; SRAM_ADDR[*] ; SW[15] ; 11.817 ; 11.862 ; Rise ; SW[15] ;; SRAM_ADDR[0] ; SW[15] ; 11.820 ; 11.862 ; Rise ; SW[15] ;; SRAM_ADDR[1] ; SW[15] ; 12.806 ; 12.890 ; Rise ; SW[15] ;; SRAM_ADDR[2] ; SW[15] ; 12.110 ; 12.187 ; Rise ; SW[15] ;; SRAM_ADDR[3] ; SW[15] ; 11.817 ; 11.865 ; Rise ; SW[15] ;; SRAM_ADDR[4] ; SW[15] ; 12.695 ; 12.809 ; Rise ; SW[15] ;; SRAM_ADDR[5] ; SW[15] ; 18.000 ; 17.818 ; Rise ; SW[15] ;; SRAM_ADDR[6] ; SW[15] ; 12.274 ; 12.287 ; Rise ; SW[15] ;; SRAM_ADDR[7] ; SW[15] ; 12.364 ; 12.395 ; Rise ; SW[15] ;; SRAM_ADDR[8] ; SW[15] ; 17.955 ; 17.895 ; Rise ; SW[15] ;; SRAM_ADDR[9] ; SW[15] ; 14.352 ; 14.061 ; Rise ; SW[15] ;; SRAM_ADDR[10] ; SW[15] ; 17.863 ; 17.869 ; Rise ; SW[15] ;; SRAM_ADDR[11] ; SW[15] ; 18.308 ; 18.275 ; Rise ; SW[15] ;; SRAM_ADDR[12] ; SW[15] ; 17.252 ; 16.927 ; Rise ; SW[15] ;; SRAM_ADDR[13] ; SW[15] ; 18.300 ; 18.296 ; Rise ; SW[15] ;; SRAM_ADDR[14] ; SW[15] ; 13.050 ; 12.980 ; Rise ; SW[15] ;; SRAM_ADDR[15] ; SW[15] ; 15.788 ; 16.374 ; Rise ; SW[15] ;; SRAM_DQ[*] ; SW[15] ; 15.032 ; 15.100 ; Rise ; SW[15] ;; SRAM_DQ[0] ; SW[15] ; 16.819 ; 16.765 ; Rise ; SW[15] ;; SRAM_DQ[1] ; SW[15] ; 16.498 ; 16.432 ; Rise ; SW[15] ;; SRAM_DQ[2] ; SW[15] ; 17.522 ; 17.450 ; Rise ; SW[15] ;; SRAM_DQ[3] ; SW[15] ; 15.895 ; 15.891 ; Rise ; SW[15] ;; SRAM_DQ[4] ; SW[15] ; 16.734 ; 16.750 ; Rise ; SW[15] ;; SRAM_DQ[5] ; SW[15] ; 15.032 ; 15.100 ; Rise ; SW[15] ;; SRAM_DQ[6] ; SW[15] ; 17.197 ; 17.265 ; Rise ; SW[15] ;; SRAM_DQ[7] ; SW[15] ; 15.995 ; 15.961 ; Rise ; SW[15] ;; SRAM_OE_N ; SW[15] ; 15.865 ; 15.481 ; Rise ; SW[15] ;; SRAM_WE_N ; SW[15] ; 13.810 ; 13.882 ; Rise ; SW[15] ;; SRAM_OE_N ; T80se:z80_inst|MREQ_n ; ; 11.313 ; Rise ; T80se:z80_inst|MREQ_n ;; SRAM_WE_N ; T80se:z80_inst|MREQ_n ; ; 9.234 ; Rise ; T80se:z80_inst|MREQ_n ;; SRAM_OE_N ; T80se:z80_inst|MREQ_n ; 11.593 ; ; Fall ; T80se:z80_inst|MREQ_n ;; SRAM_WE_N ; T80se:z80_inst|MREQ_n ; 9.044 ; ; Fall ; T80se:z80_inst|MREQ_n ;; HEX0[*] ; clk_div:clkdiv_inst|clock_100Hz ; 11.348 ; 11.355 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX0[0] ; clk_div:clkdiv_inst|clock_100Hz ; 13.545 ; 13.377 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX0[1] ; clk_div:clkdiv_inst|clock_100Hz ; 15.623 ; 15.705 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX0[2] ; clk_div:clkdiv_inst|clock_100Hz ; 13.714 ; 13.524 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX0[3] ; clk_div:clkdiv_inst|clock_100Hz ; 14.299 ; 13.884 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX0[4] ; clk_div:clkdiv_inst|clock_100Hz ; 11.348 ; 11.355 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX0[5] ; clk_div:clkdiv_inst|clock_100Hz ; 13.573 ; 13.291 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX0[6] ; clk_div:clkdiv_inst|clock_100Hz ; 12.084 ; 12.038 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX1[*] ; clk_div:clkdiv_inst|clock_100Hz ; 11.081 ; 11.011 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX1[0] ; clk_div:clkdiv_inst|clock_100Hz ; 11.458 ; 11.367 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX1[1] ; clk_div:clkdiv_inst|clock_100Hz ; 11.555 ; 11.407 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX1[2] ; clk_div:clkdiv_inst|clock_100Hz ; 12.649 ; 12.270 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX1[3] ; clk_div:clkdiv_inst|clock_100Hz ; 12.343 ; 12.004 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX1[4] ; clk_div:clkdiv_inst|clock_100Hz ; 11.081 ; 11.011 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX1[5] ; clk_div:clkdiv_inst|clock_100Hz ; 14.091 ; 13.565 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX1[6] ; clk_div:clkdiv_inst|clock_100Hz ; 13.717 ; 14.357 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX2[*] ; clk_div:clkdiv_inst|clock_100Hz ; 10.474 ; 10.435 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX2[0] ; clk_div:clkdiv_inst|clock_100Hz ; 12.315 ; 12.205 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX2[1] ; clk_div:clkdiv_inst|clock_100Hz ; 11.672 ; 11.616 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX2[2] ; clk_div:clkdiv_inst|clock_100Hz ; 12.217 ; 12.002 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX2[3] ; clk_div:clkdiv_inst|clock_100Hz ; 12.330 ; 11.985 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX2[4] ; clk_div:clkdiv_inst|clock_100Hz ; 10.474 ; 10.435 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX2[5] ; clk_div:clkdiv_inst|clock_100Hz ; 12.334 ; 11.979 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX2[6] ; clk_div:clkdiv_inst|clock_100Hz ; 12.383 ; 12.774 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX3[*] ; clk_div:clkdiv_inst|clock_100Hz ; 11.406 ; 11.304 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX3[0] ; clk_div:clkdiv_inst|clock_100Hz ; 12.696 ; 12.304 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX3[1] ; clk_div:clkdiv_inst|clock_100Hz ; 11.617 ; 11.526 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX3[2] ; clk_div:clkdiv_inst|clock_100Hz ; 13.689 ; 13.415 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX3[3] ; clk_div:clkdiv_inst|clock_100Hz ; 11.406 ; 11.304 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX3[4] ; clk_div:clkdiv_inst|clock_100Hz ; 13.500 ; 13.368 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX3[5] ; clk_div:clkdiv_inst|clock_100Hz ; 12.112 ; 12.032 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX3[6] ; clk_div:clkdiv_inst|clock_100Hz ; 12.399 ; 12.524 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX4[*] ; clk_div:clkdiv_inst|clock_100Hz ; 10.380 ; 10.434 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX4[0] ; clk_div:clkdiv_inst|clock_100Hz ; 11.241 ; 11.145 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX4[1] ; clk_div:clkdiv_inst|clock_100Hz ; 11.058 ; 10.997 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX4[2] ; clk_div:clkdiv_inst|clock_100Hz ; 10.858 ; 10.894 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX4[3] ; clk_div:clkdiv_inst|clock_100Hz ; 12.198 ; 11.956 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX4[4] ; clk_div:clkdiv_inst|clock_100Hz ; 11.329 ; 11.195 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX4[5] ; clk_div:clkdiv_inst|clock_100Hz ; 12.228 ; 12.099 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX4[6] ; clk_div:clkdiv_inst|clock_100Hz ; 10.380 ; 10.434 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX5[*] ; clk_div:clkdiv_inst|clock_100Hz ; 11.304 ; 11.126 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX5[0] ; clk_div:clkdiv_inst|clock_100Hz ; 11.609 ; 11.413 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX5[1] ; clk_div:clkdiv_inst|clock_100Hz ; 13.625 ; 13.290 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX5[2] ; clk_div:clkdiv_inst|clock_100Hz ; 12.977 ; 12.805 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX5[3] ; clk_div:clkdiv_inst|clock_100Hz ; 11.304 ; 11.126 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX5[4] ; clk_div:clkdiv_inst|clock_100Hz ; 11.865 ; 11.637 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX5[5] ; clk_div:clkdiv_inst|clock_100Hz ; 11.467 ; 11.279 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX5[6] ; clk_div:clkdiv_inst|clock_100Hz ; 11.470 ; 11.562 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX6[*] ; clk_div:clkdiv_inst|clock_100Hz ; 9.723 ; 9.544 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX6[0] ; clk_div:clkdiv_inst|clock_100Hz ; 11.157 ; 10.874 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX6[1] ; clk_div:clkdiv_inst|clock_100Hz ; 9.723 ; 9.559 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX6[2] ; clk_div:clkdiv_inst|clock_100Hz ; 9.785 ; 9.544 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX6[3] ; clk_div:clkdiv_inst|clock_100Hz ; 10.753 ; 10.573 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX6[4] ; clk_div:clkdiv_inst|clock_100Hz ; 9.868 ; 9.709 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX6[5] ; clk_div:clkdiv_inst|clock_100Hz ; 11.984 ; 11.495 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX6[6] ; clk_div:clkdiv_inst|clock_100Hz ; 9.926 ; 10.040 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX7[*] ; clk_div:clkdiv_inst|clock_100Hz ; 9.438 ; 9.288 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX7[0] ; clk_div:clkdiv_inst|clock_100Hz ; 10.326 ; 10.099 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX7[1] ; clk_div:clkdiv_inst|clock_100Hz ; 9.852 ; 9.673 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX7[2] ; clk_div:clkdiv_inst|clock_100Hz ; 9.438 ; 9.288 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX7[3] ; clk_div:clkdiv_inst|clock_100Hz ; 9.471 ; 9.324 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX7[4] ; clk_div:clkdiv_inst|clock_100Hz ; 10.057 ; 9.790 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX7[5] ; clk_div:clkdiv_inst|clock_100Hz ; 9.922 ; 9.736 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; HEX7[6] ; clk_div:clkdiv_inst|clock_100Hz ; 9.685 ; 9.852 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDG[*] ; clk_div:clkdiv_inst|clock_100Hz ; 11.074 ; 11.219 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDG[0] ; clk_div:clkdiv_inst|clock_100Hz ; 11.467 ; 11.571 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDG[1] ; clk_div:clkdiv_inst|clock_100Hz ; 11.546 ; 11.662 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDG[2] ; clk_div:clkdiv_inst|clock_100Hz ; 11.567 ; 11.680 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDG[3] ; clk_div:clkdiv_inst|clock_100Hz ; 12.284 ; 12.331 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDG[4] ; clk_div:clkdiv_inst|clock_100Hz ; 11.074 ; 11.219 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDG[5] ; clk_div:clkdiv_inst|clock_100Hz ; 11.523 ; 11.621 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDG[6] ; clk_div:clkdiv_inst|clock_100Hz ; 13.042 ; 12.912 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDG[7] ; clk_div:clkdiv_inst|clock_100Hz ; 12.268 ; 12.194 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDR[*] ; clk_div:clkdiv_inst|clock_100Hz ; 10.807 ; 10.880 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDR[0] ; clk_div:clkdiv_inst|clock_100Hz ; 12.659 ; 12.542 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDR[1] ; clk_div:clkdiv_inst|clock_100Hz ; 11.204 ; 11.321 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDR[2] ; clk_div:clkdiv_inst|clock_100Hz ; 12.789 ; 12.692 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDR[3] ; clk_div:clkdiv_inst|clock_100Hz ; 12.719 ; 12.735 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDR[4] ; clk_div:clkdiv_inst|clock_100Hz ; 11.481 ; 11.531 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDR[5] ; clk_div:clkdiv_inst|clock_100Hz ; 11.350 ; 11.389 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDR[6] ; clk_div:clkdiv_inst|clock_100Hz ; 11.555 ; 11.562 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDR[7] ; clk_div:clkdiv_inst|clock_100Hz ; 11.247 ; 11.271 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDR[8] ; clk_div:clkdiv_inst|clock_100Hz ; 13.205 ; 13.050 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDR[9] ; clk_div:clkdiv_inst|clock_100Hz ; 13.313 ; 13.458 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDR[10] ; clk_div:clkdiv_inst|clock_100Hz ; 12.624 ; 12.495 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDR[11] ; clk_div:clkdiv_inst|clock_100Hz ; 11.277 ; 11.364 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDR[12] ; clk_div:clkdiv_inst|clock_100Hz ; 10.807 ; 10.880 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDR[13] ; clk_div:clkdiv_inst|clock_100Hz ; 11.168 ; 11.194 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDR[14] ; clk_div:clkdiv_inst|clock_100Hz ; 12.717 ; 12.587 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; LEDR[15] ; clk_div:clkdiv_inst|clock_100Hz ; 14.385 ; 14.399 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_ADDR[*] ; clk_div:clkdiv_inst|clock_100Hz ; 8.365 ; 8.410 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_ADDR[0] ; clk_div:clkdiv_inst|clock_100Hz ; 8.368 ; 8.410 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_ADDR[1] ; clk_div:clkdiv_inst|clock_100Hz ; 9.354 ; 9.438 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_ADDR[2] ; clk_div:clkdiv_inst|clock_100Hz ; 8.658 ; 8.735 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_ADDR[3] ; clk_div:clkdiv_inst|clock_100Hz ; 8.365 ; 8.413 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_ADDR[4] ; clk_div:clkdiv_inst|clock_100Hz ; 9.243 ; 9.357 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_ADDR[5] ; clk_div:clkdiv_inst|clock_100Hz ; 14.548 ; 14.366 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_ADDR[6] ; clk_div:clkdiv_inst|clock_100Hz ; 8.822 ; 8.835 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_ADDR[7] ; clk_div:clkdiv_inst|clock_100Hz ; 8.912 ; 8.943 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_ADDR[8] ; clk_div:clkdiv_inst|clock_100Hz ; 14.503 ; 14.443 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_ADDR[9] ; clk_div:clkdiv_inst|clock_100Hz ; 10.900 ; 10.609 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_ADDR[10] ; clk_div:clkdiv_inst|clock_100Hz ; 14.411 ; 14.417 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_ADDR[11] ; clk_div:clkdiv_inst|clock_100Hz ; 14.856 ; 14.823 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_ADDR[12] ; clk_div:clkdiv_inst|clock_100Hz ; 13.800 ; 13.475 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_ADDR[13] ; clk_div:clkdiv_inst|clock_100Hz ; 14.848 ; 14.844 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_ADDR[14] ; clk_div:clkdiv_inst|clock_100Hz ; 9.598 ; 9.528 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_ADDR[15] ; clk_div:clkdiv_inst|clock_100Hz ; 12.336 ; 12.922 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[*] ; clk_div:clkdiv_inst|clock_100Hz ; 11.580 ; 11.648 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[0] ; clk_div:clkdiv_inst|clock_100Hz ; 13.367 ; 13.313 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[1] ; clk_div:clkdiv_inst|clock_100Hz ; 13.046 ; 12.980 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[2] ; clk_div:clkdiv_inst|clock_100Hz ; 14.070 ; 13.998 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[3] ; clk_div:clkdiv_inst|clock_100Hz ; 12.443 ; 12.439 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[4] ; clk_div:clkdiv_inst|clock_100Hz ; 13.282 ; 13.298 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[5] ; clk_div:clkdiv_inst|clock_100Hz ; 11.580 ; 11.648 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[6] ; clk_div:clkdiv_inst|clock_100Hz ; 13.745 ; 13.813 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[7] ; clk_div:clkdiv_inst|clock_100Hz ; 12.543 ; 12.509 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_OE_N ; clk_div:clkdiv_inst|clock_100Hz ; 12.413 ; 12.029 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_WE_N ; clk_div:clkdiv_inst|clock_100Hz ; 10.358 ; 10.430 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; VGA_B[*] ; clk_div:clkdiv_inst|clock_25MHz ; 10.277 ; 10.308 ; Rise ; clk_div:clkdiv_inst|clock_25MHz ;; VGA_B[4] ; clk_div:clkdiv_inst|clock_25MHz ; 11.328 ; 11.158 ; Rise ; clk_div:clkdiv_inst|clock_25MHz ;; VGA_B[5] ; clk_div:clkdiv_inst|clock_25MHz ; 10.879 ; 10.745 ; Rise ; clk_div:clkdiv_inst|clock_25MHz ;; VGA_B[6] ; clk_div:clkdiv_inst|clock_25MHz ; 10.277 ; 10.308 ; Rise ; clk_div:clkdiv_inst|clock_25MHz ;; VGA_B[7] ; clk_div:clkdiv_inst|clock_25MHz ; 11.117 ; 10.962 ; Rise ; clk_div:clkdiv_inst|clock_25MHz ;; VGA_CLK ; clk_div:clkdiv_inst|clock_25MHz ; 4.731 ; ; Rise ; clk_div:clkdiv_inst|clock_25MHz ;; VGA_HS ; clk_div:clkdiv_inst|clock_25MHz ; 9.282 ; 9.250 ; Rise ; clk_div:clkdiv_inst|clock_25MHz ;; VGA_VS ; clk_div:clkdiv_inst|clock_25MHz ; 11.272 ; 11.100 ; Rise ; clk_div:clkdiv_inst|clock_25MHz ;; VGA_CLK ; clk_div:clkdiv_inst|clock_25MHz ; ; 4.700 ; Fall ; clk_div:clkdiv_inst|clock_25MHz ;+----------------+---------------------------------+--------+--------+------------+---------------------------------++----------------------------------------------------------------------------------------------------------------+; Output Enable Times ;+-------------+---------------------------------+--------+--------+------------+---------------------------------+; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;+-------------+---------------------------------+--------+--------+------------+---------------------------------+; SRAM_DQ[*] ; SW[15] ; 15.980 ; 15.827 ; Rise ; SW[15] ;; SRAM_DQ[0] ; SW[15] ; 16.032 ; 15.879 ; Rise ; SW[15] ;; SRAM_DQ[1] ; SW[15] ; 16.082 ; 15.929 ; Rise ; SW[15] ;; SRAM_DQ[2] ; SW[15] ; 16.027 ; 15.874 ; Rise ; SW[15] ;; SRAM_DQ[3] ; SW[15] ; 16.027 ; 15.874 ; Rise ; SW[15] ;; SRAM_DQ[4] ; SW[15] ; 16.027 ; 15.874 ; Rise ; SW[15] ;; SRAM_DQ[5] ; SW[15] ; 16.019 ; 15.866 ; Rise ; SW[15] ;; SRAM_DQ[6] ; SW[15] ; 16.019 ; 15.866 ; Rise ; SW[15] ;; SRAM_DQ[7] ; SW[15] ; 15.980 ; 15.827 ; Rise ; SW[15] ;; SRAM_DQ[*] ; T80se:z80_inst|MREQ_n ; 9.746 ; 9.593 ; Rise ; T80se:z80_inst|MREQ_n ;; SRAM_DQ[0] ; T80se:z80_inst|MREQ_n ; 9.798 ; 9.645 ; Rise ; T80se:z80_inst|MREQ_n ;; SRAM_DQ[1] ; T80se:z80_inst|MREQ_n ; 9.848 ; 9.695 ; Rise ; T80se:z80_inst|MREQ_n ;; SRAM_DQ[2] ; T80se:z80_inst|MREQ_n ; 9.793 ; 9.640 ; Rise ; T80se:z80_inst|MREQ_n ;; SRAM_DQ[3] ; T80se:z80_inst|MREQ_n ; 9.793 ; 9.640 ; Rise ; T80se:z80_inst|MREQ_n ;; SRAM_DQ[4] ; T80se:z80_inst|MREQ_n ; 9.793 ; 9.640 ; Rise ; T80se:z80_inst|MREQ_n ;; SRAM_DQ[5] ; T80se:z80_inst|MREQ_n ; 9.785 ; 9.632 ; Rise ; T80se:z80_inst|MREQ_n ;; SRAM_DQ[6] ; T80se:z80_inst|MREQ_n ; 9.785 ; 9.632 ; Rise ; T80se:z80_inst|MREQ_n ;; SRAM_DQ[7] ; T80se:z80_inst|MREQ_n ; 9.746 ; 9.593 ; Rise ; T80se:z80_inst|MREQ_n ;; SRAM_DQ[*] ; clk_div:clkdiv_inst|clock_100Hz ; 11.875 ; 11.722 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[0] ; clk_div:clkdiv_inst|clock_100Hz ; 11.927 ; 11.774 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[1] ; clk_div:clkdiv_inst|clock_100Hz ; 11.977 ; 11.824 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[2] ; clk_div:clkdiv_inst|clock_100Hz ; 11.922 ; 11.769 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[3] ; clk_div:clkdiv_inst|clock_100Hz ; 11.922 ; 11.769 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[4] ; clk_div:clkdiv_inst|clock_100Hz ; 11.922 ; 11.769 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[5] ; clk_div:clkdiv_inst|clock_100Hz ; 11.914 ; 11.761 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[6] ; clk_div:clkdiv_inst|clock_100Hz ; 11.914 ; 11.761 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[7] ; clk_div:clkdiv_inst|clock_100Hz ; 11.875 ; 11.722 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;+-------------+---------------------------------+--------+--------+------------+---------------------------------++----------------------------------------------------------------------------------------------------------------+; Minimum Output Enable Times ;+-------------+---------------------------------+--------+--------+------------+---------------------------------+; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;+-------------+---------------------------------+--------+--------+------------+---------------------------------+; SRAM_DQ[*] ; SW[15] ; 14.003 ; 13.850 ; Rise ; SW[15] ;; SRAM_DQ[0] ; SW[15] ; 14.053 ; 13.900 ; Rise ; SW[15] ;; SRAM_DQ[1] ; SW[15] ; 14.100 ; 13.947 ; Rise ; SW[15] ;; SRAM_DQ[2] ; SW[15] ; 14.048 ; 13.895 ; Rise ; SW[15] ;; SRAM_DQ[3] ; SW[15] ; 14.048 ; 13.895 ; Rise ; SW[15] ;; SRAM_DQ[4] ; SW[15] ; 14.048 ; 13.895 ; Rise ; SW[15] ;; SRAM_DQ[5] ; SW[15] ; 14.040 ; 13.887 ; Rise ; SW[15] ;; SRAM_DQ[6] ; SW[15] ; 14.040 ; 13.887 ; Rise ; SW[15] ;; SRAM_DQ[7] ; SW[15] ; 14.003 ; 13.850 ; Rise ; SW[15] ;; SRAM_DQ[*] ; T80se:z80_inst|MREQ_n ; 9.355 ; 9.202 ; Rise ; T80se:z80_inst|MREQ_n ;; SRAM_DQ[0] ; T80se:z80_inst|MREQ_n ; 9.405 ; 9.252 ; Rise ; T80se:z80_inst|MREQ_n ;; SRAM_DQ[1] ; T80se:z80_inst|MREQ_n ; 9.452 ; 9.299 ; Rise ; T80se:z80_inst|MREQ_n ;; SRAM_DQ[2] ; T80se:z80_inst|MREQ_n ; 9.400 ; 9.247 ; Rise ; T80se:z80_inst|MREQ_n ;; SRAM_DQ[3] ; T80se:z80_inst|MREQ_n ; 9.400 ; 9.247 ; Rise ; T80se:z80_inst|MREQ_n ;; SRAM_DQ[4] ; T80se:z80_inst|MREQ_n ; 9.400 ; 9.247 ; Rise ; T80se:z80_inst|MREQ_n ;; SRAM_DQ[5] ; T80se:z80_inst|MREQ_n ; 9.392 ; 9.239 ; Rise ; T80se:z80_inst|MREQ_n ;; SRAM_DQ[6] ; T80se:z80_inst|MREQ_n ; 9.392 ; 9.239 ; Rise ; T80se:z80_inst|MREQ_n ;; SRAM_DQ[7] ; T80se:z80_inst|MREQ_n ; 9.355 ; 9.202 ; Rise ; T80se:z80_inst|MREQ_n ;; SRAM_DQ[*] ; clk_div:clkdiv_inst|clock_100Hz ; 10.551 ; 10.398 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[0] ; clk_div:clkdiv_inst|clock_100Hz ; 10.601 ; 10.448 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[1] ; clk_div:clkdiv_inst|clock_100Hz ; 10.648 ; 10.495 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[2] ; clk_div:clkdiv_inst|clock_100Hz ; 10.596 ; 10.443 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[3] ; clk_div:clkdiv_inst|clock_100Hz ; 10.596 ; 10.443 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[4] ; clk_div:clkdiv_inst|clock_100Hz ; 10.596 ; 10.443 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[5] ; clk_div:clkdiv_inst|clock_100Hz ; 10.588 ; 10.435 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[6] ; clk_div:clkdiv_inst|clock_100Hz ; 10.588 ; 10.435 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[7] ; clk_div:clkdiv_inst|clock_100Hz ; 10.551 ; 10.398 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;+-------------+---------------------------------+--------+--------+------------+---------------------------------++----------------------------------------------------------------------------------------------------------------------+; Output Disable Times ;+-------------+---------------------------------+-----------+-----------+------------+---------------------------------+; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ;+-------------+---------------------------------+-----------+-----------+------------+---------------------------------+; SRAM_DQ[*] ; SW[15] ; 15.819 ; 15.972 ; Rise ; SW[15] ;; SRAM_DQ[0] ; SW[15] ; 15.881 ; 16.034 ; Rise ; SW[15] ;; SRAM_DQ[1] ; SW[15] ; 15.931 ; 16.084 ; Rise ; SW[15] ;; SRAM_DQ[2] ; SW[15] ; 15.875 ; 16.028 ; Rise ; SW[15] ;; SRAM_DQ[3] ; SW[15] ; 15.875 ; 16.028 ; Rise ; SW[15] ;; SRAM_DQ[4] ; SW[15] ; 15.875 ; 16.028 ; Rise ; SW[15] ;; SRAM_DQ[5] ; SW[15] ; 15.861 ; 16.014 ; Rise ; SW[15] ;; SRAM_DQ[6] ; SW[15] ; 15.861 ; 16.014 ; Rise ; SW[15] ;; SRAM_DQ[7] ; SW[15] ; 15.819 ; 15.972 ; Rise ; SW[15] ;; SRAM_DQ[*] ; T80se:z80_inst|MREQ_n ; 9.542 ; 9.695 ; Fall ; T80se:z80_inst|MREQ_n ;; SRAM_DQ[0] ; T80se:z80_inst|MREQ_n ; 9.604 ; 9.757 ; Fall ; T80se:z80_inst|MREQ_n ;; SRAM_DQ[1] ; T80se:z80_inst|MREQ_n ; 9.654 ; 9.807 ; Fall ; T80se:z80_inst|MREQ_n ;; SRAM_DQ[2] ; T80se:z80_inst|MREQ_n ; 9.598 ; 9.751 ; Fall ; T80se:z80_inst|MREQ_n ;; SRAM_DQ[3] ; T80se:z80_inst|MREQ_n ; 9.598 ; 9.751 ; Fall ; T80se:z80_inst|MREQ_n ;; SRAM_DQ[4] ; T80se:z80_inst|MREQ_n ; 9.598 ; 9.751 ; Fall ; T80se:z80_inst|MREQ_n ;; SRAM_DQ[5] ; T80se:z80_inst|MREQ_n ; 9.584 ; 9.737 ; Fall ; T80se:z80_inst|MREQ_n ;; SRAM_DQ[6] ; T80se:z80_inst|MREQ_n ; 9.584 ; 9.737 ; Fall ; T80se:z80_inst|MREQ_n ;; SRAM_DQ[7] ; T80se:z80_inst|MREQ_n ; 9.542 ; 9.695 ; Fall ; T80se:z80_inst|MREQ_n ;; SRAM_DQ[*] ; clk_div:clkdiv_inst|clock_100Hz ; 11.714 ; 11.867 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[0] ; clk_div:clkdiv_inst|clock_100Hz ; 11.776 ; 11.929 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[1] ; clk_div:clkdiv_inst|clock_100Hz ; 11.826 ; 11.979 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[2] ; clk_div:clkdiv_inst|clock_100Hz ; 11.770 ; 11.923 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[3] ; clk_div:clkdiv_inst|clock_100Hz ; 11.770 ; 11.923 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[4] ; clk_div:clkdiv_inst|clock_100Hz ; 11.770 ; 11.923 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[5] ; clk_div:clkdiv_inst|clock_100Hz ; 11.756 ; 11.909 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[6] ; clk_div:clkdiv_inst|clock_100Hz ; 11.756 ; 11.909 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[7] ; clk_div:clkdiv_inst|clock_100Hz ; 11.714 ; 11.867 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;+-------------+---------------------------------+-----------+-----------+------------+---------------------------------++----------------------------------------------------------------------------------------------------------------------+; Minimum Output Disable Times ;+-------------+---------------------------------+-----------+-----------+------------+---------------------------------+; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ;+-------------+---------------------------------+-----------+-----------+------------+---------------------------------+; SRAM_DQ[*] ; SW[15] ; 13.918 ; 14.071 ; Rise ; SW[15] ;; SRAM_DQ[0] ; SW[15] ; 13.977 ; 14.130 ; Rise ; SW[15] ;; SRAM_DQ[1] ; SW[15] ; 14.025 ; 14.178 ; Rise ; SW[15] ;; SRAM_DQ[2] ; SW[15] ; 13.972 ; 14.125 ; Rise ; SW[15] ;; SRAM_DQ[3] ; SW[15] ; 13.972 ; 14.125 ; Rise ; SW[15] ;; SRAM_DQ[4] ; SW[15] ; 13.972 ; 14.125 ; Rise ; SW[15] ;; SRAM_DQ[5] ; SW[15] ; 13.958 ; 14.111 ; Rise ; SW[15] ;; SRAM_DQ[6] ; SW[15] ; 13.958 ; 14.111 ; Rise ; SW[15] ;; SRAM_DQ[7] ; SW[15] ; 13.918 ; 14.071 ; Rise ; SW[15] ;; SRAM_DQ[*] ; T80se:z80_inst|MREQ_n ; 9.152 ; 9.305 ; Fall ; T80se:z80_inst|MREQ_n ;; SRAM_DQ[0] ; T80se:z80_inst|MREQ_n ; 9.211 ; 9.364 ; Fall ; T80se:z80_inst|MREQ_n ;; SRAM_DQ[1] ; T80se:z80_inst|MREQ_n ; 9.259 ; 9.412 ; Fall ; T80se:z80_inst|MREQ_n ;; SRAM_DQ[2] ; T80se:z80_inst|MREQ_n ; 9.206 ; 9.359 ; Fall ; T80se:z80_inst|MREQ_n ;; SRAM_DQ[3] ; T80se:z80_inst|MREQ_n ; 9.206 ; 9.359 ; Fall ; T80se:z80_inst|MREQ_n ;; SRAM_DQ[4] ; T80se:z80_inst|MREQ_n ; 9.206 ; 9.359 ; Fall ; T80se:z80_inst|MREQ_n ;; SRAM_DQ[5] ; T80se:z80_inst|MREQ_n ; 9.192 ; 9.345 ; Fall ; T80se:z80_inst|MREQ_n ;; SRAM_DQ[6] ; T80se:z80_inst|MREQ_n ; 9.192 ; 9.345 ; Fall ; T80se:z80_inst|MREQ_n ;; SRAM_DQ[7] ; T80se:z80_inst|MREQ_n ; 9.152 ; 9.305 ; Fall ; T80se:z80_inst|MREQ_n ;; SRAM_DQ[*] ; clk_div:clkdiv_inst|clock_100Hz ; 10.466 ; 10.619 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[0] ; clk_div:clkdiv_inst|clock_100Hz ; 10.525 ; 10.678 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[1] ; clk_div:clkdiv_inst|clock_100Hz ; 10.573 ; 10.726 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[2] ; clk_div:clkdiv_inst|clock_100Hz ; 10.520 ; 10.673 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[3] ; clk_div:clkdiv_inst|clock_100Hz ; 10.520 ; 10.673 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[4] ; clk_div:clkdiv_inst|clock_100Hz ; 10.520 ; 10.673 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[5] ; clk_div:clkdiv_inst|clock_100Hz ; 10.506 ; 10.659 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[6] ; clk_div:clkdiv_inst|clock_100Hz ; 10.506 ; 10.659 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;; SRAM_DQ[7] ; clk_div:clkdiv_inst|clock_100Hz ; 10.466 ; 10.619 ; Rise ; clk_div:clkdiv_inst|clock_100Hz ;+-------------+---------------------------------+-----------+-----------+------------+---------------------------------+------------------------; Metastability Report ;------------------------No synchronizer chains to report.+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Board Trace Model Assignments ;+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+; HEX0[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX0[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX0[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX0[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX0[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX0[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX0[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX1[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX1[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX1[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX1[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX1[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX1[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX1[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX2[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX2[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX2[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX2[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX2[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX2[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX2[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX3[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX3[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX3[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX3[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX3[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX3[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX3[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX4[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX4[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX4[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX4[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX4[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX4[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX4[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX5[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX5[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX5[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX5[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX5[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX5[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX5[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX6[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX6[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX6[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX6[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX6[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX6[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX6[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX7[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX7[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX7[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX7[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX7[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX7[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; HEX7[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LEDG[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LEDG[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LEDG[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LEDG[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LEDG[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LEDG[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LEDG[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LEDG[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LEDG[8] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LEDR[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LEDR[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LEDR[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LEDR[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LEDR[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LEDR[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LEDR[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LEDR[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LEDR[8] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LEDR[9] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LEDR[10] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LEDR[11] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LEDR[12] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LEDR[13] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LEDR[14] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LEDR[15] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LEDR[16] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LEDR[17] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; UART_TXD ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_BA_0 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_BA_1 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_DQM_0 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_DQM_1 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_DQM_2 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_DQM_3 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_WE_N ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_CAS_N ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_RAS_N ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_CS_N ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_ADDR[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_ADDR[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_ADDR[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_ADDR[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_ADDR[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_ADDR[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_ADDR[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_ADDR[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_ADDR[8] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_ADDR[9] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_ADDR[10] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_ADDR[11] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_ADDR[12] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_CLK ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_CKE ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; FL_ADDR[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; FL_ADDR[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; FL_ADDR[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; FL_ADDR[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; FL_ADDR[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; FL_ADDR[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; FL_ADDR[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; FL_ADDR[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; FL_ADDR[8] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; FL_ADDR[9] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; FL_ADDR[10] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; FL_ADDR[11] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; FL_ADDR[12] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; FL_ADDR[13] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; FL_ADDR[14] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; FL_ADDR[15] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; FL_ADDR[16] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; FL_ADDR[17] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; FL_ADDR[18] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; FL_ADDR[19] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; FL_ADDR[20] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; FL_ADDR[21] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; FL_ADDR[22] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; FL_WP_N ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; FL_WE_N ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; FL_RST_N ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; FL_OE_N ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; FL_CE_N ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_ADDR[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_ADDR[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_ADDR[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_ADDR[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_ADDR[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_ADDR[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_ADDR[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_ADDR[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_ADDR[8] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_ADDR[9] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_ADDR[10] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_ADDR[11] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_ADDR[12] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_ADDR[13] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_ADDR[14] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_ADDR[15] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_ADDR[16] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_ADDR[17] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_ADDR[18] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_ADDR[19] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_UB_N ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_LB_N ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_WE_N ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_CE_N ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_OE_N ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SD_DAT3 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SD_CMD ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SD_CLK ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; VGA_SYNC_N ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; VGA_CLK ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; VGA_BLANK_N ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; VGA_HS ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; VGA_VS ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; VGA_R[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; VGA_R[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; VGA_R[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; VGA_R[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; VGA_R[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; VGA_R[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; VGA_R[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; VGA_R[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; VGA_G[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; VGA_G[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; VGA_G[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; VGA_G[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; VGA_G[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; VGA_G[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; VGA_G[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; VGA_G[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; VGA_B[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; VGA_B[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; VGA_B[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; VGA_B[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; VGA_B[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; VGA_B[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; VGA_B[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; VGA_B[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; AUD_DACDAT ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; AUD_XCK ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LCD_RS ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LCD_EN ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LCD_RW ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LCD_ON ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LCD_BLON ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SD_DAT1 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SD_DAT2 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; PS2_DAT2 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; PS2_CLK2 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_DQ[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_DQ[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_DQ[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_DQ[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_DQ[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_DQ[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_DQ[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_DQ[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_DQ[8] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_DQ[9] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_DQ[10] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_DQ[11] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_DQ[12] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_DQ[13] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_DQ[14] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_DQ[15] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_DQ[16] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_DQ[17] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_DQ[18] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_DQ[19] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_DQ[20] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_DQ[21] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_DQ[22] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_DQ[23] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_DQ[24] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_DQ[25] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_DQ[26] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_DQ[27] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_DQ[28] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_DQ[29] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_DQ[30] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; DRAM_DQ[31] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; FL_DQ[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; FL_DQ[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; FL_DQ[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; FL_DQ[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; FL_DQ[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; FL_DQ[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; FL_DQ[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; FL_DQ[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_DQ[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_DQ[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_DQ[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_DQ[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_DQ[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_DQ[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_DQ[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_DQ[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_DQ[8] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_DQ[9] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_DQ[10] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_DQ[11] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_DQ[12] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_DQ[13] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_DQ[14] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; SRAM_DQ[15] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; PS2_DAT ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; PS2_CLK ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; AUD_ADCLRCK ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; AUD_DACLRCK ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; AUD_BCLK ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LCD_DATA[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LCD_DATA[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LCD_DATA[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LCD_DATA[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LCD_DATA[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LCD_DATA[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LCD_DATA[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LCD_DATA[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; ~ALTERA_nCEO~ ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------++----------------------------------------------------------------------------+; Input Transition Times ;+-------------------------+--------------+-----------------+-----------------+; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;+-------------------------+--------------+-----------------+-----------------+; UART_RXD ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; UART_RTS ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; UART_CTS ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; FL_RY ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; SD_DAT0 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; AUD_ADCDAT ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; SD_DAT1 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; SD_DAT2 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; PS2_DAT2 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; PS2_CLK2 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; DRAM_DQ[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; DRAM_DQ[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; DRAM_DQ[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; DRAM_DQ[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; DRAM_DQ[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; DRAM_DQ[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; DRAM_DQ[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; DRAM_DQ[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; DRAM_DQ[8] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; DRAM_DQ[9] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; DRAM_DQ[10] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; DRAM_DQ[11] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; DRAM_DQ[12] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; DRAM_DQ[13] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; DRAM_DQ[14] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; DRAM_DQ[15] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; DRAM_DQ[16] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; DRAM_DQ[17] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; DRAM_DQ[18] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; DRAM_DQ[19] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; DRAM_DQ[20] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; DRAM_DQ[21] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; DRAM_DQ[22] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; DRAM_DQ[23] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; DRAM_DQ[24] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; DRAM_DQ[25] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; DRAM_DQ[26] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; DRAM_DQ[27] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; DRAM_DQ[28] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; DRAM_DQ[29] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; DRAM_DQ[30] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; DRAM_DQ[31] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; FL_DQ[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; FL_DQ[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; FL_DQ[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; FL_DQ[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; FL_DQ[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; FL_DQ[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; FL_DQ[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; FL_DQ[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; SRAM_DQ[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; SRAM_DQ[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; SRAM_DQ[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; SRAM_DQ[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; SRAM_DQ[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; SRAM_DQ[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; SRAM_DQ[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; SRAM_DQ[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; SRAM_DQ[8] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; SRAM_DQ[9] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; SRAM_DQ[10] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; SRAM_DQ[11] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; SRAM_DQ[12] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; SRAM_DQ[13] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; SRAM_DQ[14] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; SRAM_DQ[15] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; PS2_DAT ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; PS2_CLK ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; AUD_ADCLRCK ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; AUD_DACLRCK ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; AUD_BCLK ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; LCD_DATA[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; LCD_DATA[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; LCD_DATA[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; LCD_DATA[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; LCD_DATA[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; LCD_DATA[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; LCD_DATA[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; LCD_DATA[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; SW[17] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; CLOCK_50 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; SW[14] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; SW[15] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; SW[16] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; SW[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; SW[9] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; KEY[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; SW[8] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; SW[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; KEY[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; SW[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; SW[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; SW[10] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; SW[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; KEY[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; SW[13] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; SW[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; SW[12] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; SW[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; SW[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; SW[11] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; KEY[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; ~ALTERA_ASDO_DATA1~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; ~ALTERA_DATA0~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;+-------------------------+--------------+-----------------+-----------------++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Signal Integrity Metrics (Slow 1200mv 85c Model) ;+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.33 V ; -0.00265 V ; 0.133 V ; 0.056 V ; 3.55e-09 s ; 3.31e-09 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.33 V ; -0.00265 V ; 0.133 V ; 0.056 V ; 3.55e-09 s ; 3.31e-09 s ; Yes ; Yes ;; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;; HEX0[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.12 V ; -0.0722 V ; 0.214 V ; 0.171 V ; 6.67e-10 s ; 6.2e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.12 V ; -0.0722 V ; 0.214 V ; 0.171 V ; 6.67e-10 s ; 6.2e-10 s ; Yes ; No ;; HEX0[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.12 V ; -0.0722 V ; 0.214 V ; 0.171 V ; 6.67e-10 s ; 6.2e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.12 V ; -0.0722 V ; 0.214 V ; 0.171 V ; 6.67e-10 s ; 6.2e-10 s ; Yes ; No ;; HEX0[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.08 V ; -0.00641 V ; 0.261 V ; 0.26 V ; 5.52e-09 s ; 4.36e-09 s ; Yes ; Yes ; 3.08 V ; 1.28e-06 V ; 3.08 V ; -0.00641 V ; 0.261 V ; 0.26 V ; 5.52e-09 s ; 4.36e-09 s ; Yes ; Yes ;; HEX0[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.12 V ; -0.0722 V ; 0.214 V ; 0.171 V ; 6.67e-10 s ; 6.2e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.12 V ; -0.0722 V ; 0.214 V ; 0.171 V ; 6.67e-10 s ; 6.2e-10 s ; Yes ; No ;; HEX1[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.12 V ; -0.0722 V ; 0.214 V ; 0.171 V ; 6.67e-10 s ; 6.2e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.12 V ; -0.0722 V ; 0.214 V ; 0.171 V ; 6.67e-10 s ; 6.2e-10 s ; Yes ; No ;; HEX1[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; HEX1[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; HEX1[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; HEX1[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; HEX1[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.08 V ; -0.00641 V ; 0.261 V ; 0.26 V ; 5.52e-09 s ; 4.36e-09 s ; Yes ; Yes ; 3.08 V ; 1.28e-06 V ; 3.08 V ; -0.00641 V ; 0.261 V ; 0.26 V ; 5.52e-09 s ; 4.36e-09 s ; Yes ; Yes ;; HEX1[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.08 V ; -0.00641 V ; 0.261 V ; 0.26 V ; 5.52e-09 s ; 4.36e-09 s ; Yes ; Yes ; 3.08 V ; 1.28e-06 V ; 3.08 V ; -0.00641 V ; 0.261 V ; 0.26 V ; 5.52e-09 s ; 4.36e-09 s ; Yes ; Yes ;; HEX2[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; HEX2[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; HEX2[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; HEX2[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; HEX2[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; HEX2[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; HEX2[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; HEX3[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; HEX3[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.12 V ; -0.0722 V ; 0.214 V ; 0.171 V ; 6.67e-10 s ; 6.2e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.12 V ; -0.0722 V ; 0.214 V ; 0.171 V ; 6.67e-10 s ; 6.2e-10 s ; Yes ; No ;; HEX3[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.08 V ; -0.00581 V ; 0.138 V ; 0.22 V ; 5.55e-09 s ; 4.38e-09 s ; Yes ; Yes ; 3.08 V ; 1.9e-06 V ; 3.08 V ; -0.00581 V ; 0.138 V ; 0.22 V ; 5.55e-09 s ; 4.38e-09 s ; Yes ; Yes ;; HEX3[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; HEX3[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; HEX3[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; HEX3[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; HEX4[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; HEX4[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; HEX4[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; HEX4[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; HEX4[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; HEX4[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; HEX4[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; HEX5[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; HEX5[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.08 V ; -0.00581 V ; 0.138 V ; 0.22 V ; 5.55e-09 s ; 4.38e-09 s ; Yes ; Yes ; 3.08 V ; 1.9e-06 V ; 3.08 V ; -0.00581 V ; 0.138 V ; 0.22 V ; 5.55e-09 s ; 4.38e-09 s ; Yes ; Yes ;; HEX5[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; HEX5[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; HEX5[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; HEX5[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; HEX5[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; HEX6[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; HEX6[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; HEX6[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; HEX6[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; HEX6[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; HEX6[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.08 V ; -0.00581 V ; 0.138 V ; 0.22 V ; 5.55e-09 s ; 4.38e-09 s ; Yes ; Yes ; 3.08 V ; 1.9e-06 V ; 3.08 V ; -0.00581 V ; 0.138 V ; 0.22 V ; 5.55e-09 s ; 4.38e-09 s ; Yes ; Yes ;; HEX6[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; HEX7[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; HEX7[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; HEX7[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; HEX7[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; HEX7[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; HEX7[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; HEX7[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; LEDG[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;; LEDG[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;; LEDG[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;; LEDG[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;; LEDG[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;; LEDG[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;; LEDG[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;; LEDG[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;; LEDG[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.33 V ; -0.00265 V ; 0.133 V ; 0.056 V ; 3.55e-09 s ; 3.31e-09 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.33 V ; -0.00265 V ; 0.133 V ; 0.056 V ; 3.55e-09 s ; 3.31e-09 s ; Yes ; Yes ;; LEDR[10] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;; LEDR[11] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;; LEDR[12] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;; LEDR[13] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;; LEDR[14] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;; LEDR[15] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.33 V ; -0.00265 V ; 0.133 V ; 0.056 V ; 3.55e-09 s ; 3.31e-09 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.33 V ; -0.00265 V ; 0.133 V ; 0.056 V ; 3.55e-09 s ; 3.31e-09 s ; Yes ; Yes ;; LEDR[16] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;; LEDR[17] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;; UART_TXD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.08 V ; -0.00581 V ; 0.138 V ; 0.22 V ; 5.55e-09 s ; 4.38e-09 s ; Yes ; Yes ; 3.08 V ; 1.9e-06 V ; 3.08 V ; -0.00581 V ; 0.138 V ; 0.22 V ; 5.55e-09 s ; 4.38e-09 s ; Yes ; Yes ;; DRAM_BA_0 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.12 V ; -0.0722 V ; 0.214 V ; 0.171 V ; 6.67e-10 s ; 6.2e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.12 V ; -0.0722 V ; 0.214 V ; 0.171 V ; 6.67e-10 s ; 6.2e-10 s ; Yes ; No ;; DRAM_BA_1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_DQM_0 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_DQM_1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_DQM_2 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_DQM_3 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.12 V ; -0.0722 V ; 0.214 V ; 0.171 V ; 6.67e-10 s ; 6.2e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.12 V ; -0.0722 V ; 0.214 V ; 0.171 V ; 6.67e-10 s ; 6.2e-10 s ; Yes ; No ;; DRAM_WE_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_CAS_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_RAS_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_CS_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_ADDR[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_ADDR[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_ADDR[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.12 V ; -0.0722 V ; 0.214 V ; 0.171 V ; 6.67e-10 s ; 6.2e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.12 V ; -0.0722 V ; 0.214 V ; 0.171 V ; 6.67e-10 s ; 6.2e-10 s ; Yes ; No ;; DRAM_ADDR[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_ADDR[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_ADDR[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_ADDR[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.12 V ; -0.0722 V ; 0.214 V ; 0.171 V ; 6.67e-10 s ; 6.2e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.12 V ; -0.0722 V ; 0.214 V ; 0.171 V ; 6.67e-10 s ; 6.2e-10 s ; Yes ; No ;; DRAM_ADDR[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.12 V ; -0.0722 V ; 0.214 V ; 0.171 V ; 6.67e-10 s ; 6.2e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.12 V ; -0.0722 V ; 0.214 V ; 0.171 V ; 6.67e-10 s ; 6.2e-10 s ; Yes ; No ;; DRAM_ADDR[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_ADDR[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_ADDR[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.12 V ; -0.0722 V ; 0.214 V ; 0.171 V ; 6.67e-10 s ; 6.2e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.12 V ; -0.0722 V ; 0.214 V ; 0.171 V ; 6.67e-10 s ; 6.2e-10 s ; Yes ; No ;; DRAM_ADDR[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_ADDR[12] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_CLK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; DRAM_CKE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; FL_ADDR[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; FL_ADDR[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; FL_ADDR[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; FL_ADDR[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; FL_ADDR[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; FL_ADDR[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; FL_ADDR[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; FL_ADDR[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.08 V ; -0.00581 V ; 0.138 V ; 0.22 V ; 5.55e-09 s ; 4.38e-09 s ; Yes ; Yes ; 3.08 V ; 1.9e-06 V ; 3.08 V ; -0.00581 V ; 0.138 V ; 0.22 V ; 5.55e-09 s ; 4.38e-09 s ; Yes ; Yes ;; FL_ADDR[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; FL_ADDR[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; FL_ADDR[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; FL_ADDR[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; FL_ADDR[12] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; FL_ADDR[13] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; FL_ADDR[14] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; FL_ADDR[15] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.08 V ; -0.00581 V ; 0.138 V ; 0.22 V ; 5.55e-09 s ; 4.38e-09 s ; Yes ; Yes ; 3.08 V ; 1.9e-06 V ; 3.08 V ; -0.00581 V ; 0.138 V ; 0.22 V ; 5.55e-09 s ; 4.38e-09 s ; Yes ; Yes ;; FL_ADDR[16] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; FL_ADDR[17] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; FL_ADDR[18] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; FL_ADDR[19] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; FL_ADDR[20] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; FL_ADDR[21] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; FL_ADDR[22] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; FL_WP_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; FL_WE_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; FL_RST_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; FL_OE_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; FL_CE_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; SRAM_ADDR[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; SRAM_ADDR[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; SRAM_ADDR[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; SRAM_ADDR[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; SRAM_ADDR[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; SRAM_ADDR[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; SRAM_ADDR[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; SRAM_ADDR[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; SRAM_ADDR[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; SRAM_ADDR[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.08 V ; -0.00641 V ; 0.261 V ; 0.26 V ; 5.52e-09 s ; 4.36e-09 s ; Yes ; Yes ; 3.08 V ; 1.28e-06 V ; 3.08 V ; -0.00641 V ; 0.261 V ; 0.26 V ; 5.52e-09 s ; 4.36e-09 s ; Yes ; Yes ;; SRAM_ADDR[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; SRAM_ADDR[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; SRAM_ADDR[12] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.08 V ; -0.00641 V ; 0.261 V ; 0.26 V ; 5.52e-09 s ; 4.36e-09 s ; Yes ; Yes ; 3.08 V ; 1.28e-06 V ; 3.08 V ; -0.00641 V ; 0.261 V ; 0.26 V ; 5.52e-09 s ; 4.36e-09 s ; Yes ; Yes ;; SRAM_ADDR[13] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; SRAM_ADDR[14] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; SRAM_ADDR[15] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.08 V ; -0.00581 V ; 0.138 V ; 0.22 V ; 5.55e-09 s ; 4.38e-09 s ; Yes ; Yes ; 3.08 V ; 1.9e-06 V ; 3.08 V ; -0.00581 V ; 0.138 V ; 0.22 V ; 5.55e-09 s ; 4.38e-09 s ; Yes ; Yes ;; SRAM_ADDR[16] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; SRAM_ADDR[17] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; SRAM_ADDR[18] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; SRAM_ADDR[19] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.08 V ; -0.00641 V ; 0.261 V ; 0.26 V ; 5.52e-09 s ; 4.36e-09 s ; Yes ; Yes ; 3.08 V ; 1.28e-06 V ; 3.08 V ; -0.00641 V ; 0.261 V ; 0.26 V ; 5.52e-09 s ; 4.36e-09 s ; Yes ; Yes ;; SRAM_UB_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; SRAM_LB_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; SRAM_WE_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; SRAM_CE_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; SRAM_OE_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; SD_DAT3 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; SD_CMD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; SD_CLK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; VGA_SYNC_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; VGA_CLK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; VGA_BLANK_N ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; VGA_HS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; VGA_VS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; VGA_R[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; VGA_R[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; VGA_R[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; VGA_R[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; VGA_R[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; VGA_R[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; VGA_R[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; VGA_R[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; VGA_G[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; VGA_G[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; VGA_G[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; VGA_G[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; VGA_G[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; VGA_G[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; VGA_G[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; VGA_G[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; VGA_B[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; VGA_B[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; VGA_B[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; VGA_B[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; VGA_B[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; VGA_B[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; VGA_B[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; VGA_B[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; AUD_DACDAT ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; AUD_XCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; LCD_RS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; LCD_EN ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; LCD_RW ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; LCD_ON ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; LCD_BLON ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; SD_DAT1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; SD_DAT2 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; PS2_DAT2 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; PS2_CLK2 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_DQ[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_DQ[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_DQ[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_DQ[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_DQ[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_DQ[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_DQ[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_DQ[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_DQ[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_DQ[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_DQ[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_DQ[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_DQ[12] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_DQ[13] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_DQ[14] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.12 V ; -0.0722 V ; 0.214 V ; 0.171 V ; 6.67e-10 s ; 6.2e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.12 V ; -0.0722 V ; 0.214 V ; 0.171 V ; 6.67e-10 s ; 6.2e-10 s ; Yes ; No ;; DRAM_DQ[15] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_DQ[16] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_DQ[17] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_DQ[18] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_DQ[19] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_DQ[20] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_DQ[21] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_DQ[22] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_DQ[23] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_DQ[24] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_DQ[25] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_DQ[26] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_DQ[27] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_DQ[28] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_DQ[29] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_DQ[30] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; DRAM_DQ[31] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; FL_DQ[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; FL_DQ[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; FL_DQ[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; FL_DQ[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; FL_DQ[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; FL_DQ[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; FL_DQ[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; FL_DQ[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; SRAM_DQ[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; SRAM_DQ[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; SRAM_DQ[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; SRAM_DQ[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; SRAM_DQ[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; SRAM_DQ[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; SRAM_DQ[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; SRAM_DQ[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; SRAM_DQ[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; SRAM_DQ[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; SRAM_DQ[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; SRAM_DQ[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; SRAM_DQ[12] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; SRAM_DQ[13] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; SRAM_DQ[14] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; SRAM_DQ[15] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; PS2_DAT ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.12 V ; -0.0722 V ; 0.214 V ; 0.171 V ; 6.67e-10 s ; 6.2e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.12 V ; -0.0722 V ; 0.214 V ; 0.171 V ; 6.67e-10 s ; 6.2e-10 s ; Yes ; No ;; PS2_CLK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; AUD_ADCLRCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; AUD_DACLRCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; AUD_BCLK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;; LCD_DATA[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; LCD_DATA[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; LCD_DATA[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; LCD_DATA[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; LCD_DATA[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; LCD_DATA[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; LCD_DATA[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; LCD_DATA[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ;; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 6.54e-07 V ; 3.14 V ; -0.115 V ; 0.146 V ; 0.141 V ; 3.07e-10 s ; 3.96e-10 s ; Yes ; No ; 3.08 V ; 6.54e-07 V ; 3.14 V ; -0.115 V ; 0.146 V ; 0.141 V ; 3.07e-10 s ; 3.96e-10 s ; Yes ; No ;; ~ALTERA_nCEO~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ;+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Setup Transfers ;+-------------------------------------------------------------+-------------------------------------------------------------+----------+----------+----------+----------+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;+-------------------------------------------------------------+-------------------------------------------------------------+----------+----------+----------+----------+; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; 12 ; 0 ; 0 ; 0 ;; clk_div:clkdiv_inst|clock_1Mhz_int ; clk_div:clkdiv_inst|clock_1Mhz_int ; 11 ; 0 ; 0 ; 0 ;; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_1Mhz_int ; 1 ; 1 ; 0 ; 0 ;; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; 1 ; 1 ; 0 ; 0 ;; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; 11 ; 0 ; 0 ; 0 ;; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 2611 ; 0 ; 0 ; 0 ;; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 225 ; 0 ; 0 ; 0 ;; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 225 ; 0 ; 0 ; 0 ;; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 28 ; 0 ; 0 ; 0 ;; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_100Hz ; 60 ; 0 ; 0 ; 0 ;; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_100Hz ; 5829022 ; 0 ; 0 ; 0 ;; CLOCK_50 ; clk_div:clkdiv_inst|clock_100Hz ; 288 ; 0 ; 0 ; 0 ;; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; clk_div:clkdiv_inst|clock_100Hz ; 16 ; 0 ; 0 ; 0 ;; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 5829022 ; 2 ; 0 ; 0 ;; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 754 ; 1010 ; 0 ; 0 ;; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; 1 ; 1 ; 0 ; 0 ;; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; 11 ; 0 ; 0 ; 0 ;; clk_div:clkdiv_inst|clock_1Khz_int ; CLOCK_50 ; 2 ; 1 ; 0 ; 0 ;; clk_div:clkdiv_inst|clock_25Mhz_int ; CLOCK_50 ; 2 ; 2 ; 0 ; 0 ;; clk_div:clkdiv_inst|clock_100Hz ; CLOCK_50 ; 517 ; 0 ; 0 ; 0 ;; CLOCK_50 ; CLOCK_50 ; 978 ; 0 ; 0 ; 0 ;; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50 ; 3338 ; 3 ; 0 ; 0 ;; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set ; CLOCK_50 ; 9 ; 0 ; 0 ; 0 ;; SW[15] ; CLOCK_50 ; 117 ; 0 ; 0 ; 0 ;; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 141 ; 0 ; 0 ; 0 ;; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1 ; 1 ; 0 ; 0 ;; clk_div:clkdiv_inst|clock_25MHz ; SW[15] ; 60 ; 0 ; 0 ; 0 ;; clk_div:clkdiv_inst|clock_100Hz ; SW[15] ; 5829020 ; 0 ; 0 ; 0 ;; CLOCK_50 ; SW[15] ; 288 ; 0 ; 0 ; 0 ;; SW[15] ; SW[15] ; 5829022 ; 2 ; 0 ; 0 ;; T80se:z80_inst|MREQ_n ; SW[15] ; 754 ; 1010 ; 0 ; 0 ;; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; 0 ; 0 ; 256 ; 0 ;; SW[15] ; T80se:z80_inst|MREQ_n ; 0 ; 0 ; 256 ; 0 ;+-------------------------------------------------------------+-------------------------------------------------------------+----------+----------+----------+----------+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Hold Transfers ;+-------------------------------------------------------------+-------------------------------------------------------------+----------+----------+----------+----------+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;+-------------------------------------------------------------+-------------------------------------------------------------+----------+----------+----------+----------+; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_1Khz_int ; 12 ; 0 ; 0 ; 0 ;; clk_div:clkdiv_inst|clock_1Mhz_int ; clk_div:clkdiv_inst|clock_1Mhz_int ; 11 ; 0 ; 0 ; 0 ;; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_1Mhz_int ; 1 ; 1 ; 0 ; 0 ;; clk_div:clkdiv_inst|clock_1Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; 1 ; 1 ; 0 ; 0 ;; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_10Khz_int ; 11 ; 0 ; 0 ; 0 ;; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 2611 ; 0 ; 0 ; 0 ;; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_25MHz ; 225 ; 0 ; 0 ; 0 ;; SW[15] ; clk_div:clkdiv_inst|clock_25MHz ; 225 ; 0 ; 0 ; 0 ;; clk_div:clkdiv_inst|clock_25Mhz_int ; clk_div:clkdiv_inst|clock_25Mhz_int ; 28 ; 0 ; 0 ; 0 ;; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_100Hz ; 60 ; 0 ; 0 ; 0 ;; clk_div:clkdiv_inst|clock_100Hz ; clk_div:clkdiv_inst|clock_100Hz ; 5829022 ; 0 ; 0 ; 0 ;; CLOCK_50 ; clk_div:clkdiv_inst|clock_100Hz ; 288 ; 0 ; 0 ; 0 ;; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; clk_div:clkdiv_inst|clock_100Hz ; 16 ; 0 ; 0 ; 0 ;; SW[15] ; clk_div:clkdiv_inst|clock_100Hz ; 5829022 ; 2 ; 0 ; 0 ;; T80se:z80_inst|MREQ_n ; clk_div:clkdiv_inst|clock_100Hz ; 754 ; 1010 ; 0 ; 0 ;; clk_div:clkdiv_inst|clock_10Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; 1 ; 1 ; 0 ; 0 ;; clk_div:clkdiv_inst|clock_100Khz_int ; clk_div:clkdiv_inst|clock_100Khz_int ; 11 ; 0 ; 0 ; 0 ;; clk_div:clkdiv_inst|clock_1Khz_int ; CLOCK_50 ; 2 ; 1 ; 0 ; 0 ;; clk_div:clkdiv_inst|clock_25Mhz_int ; CLOCK_50 ; 2 ; 2 ; 0 ; 0 ;; clk_div:clkdiv_inst|clock_100Hz ; CLOCK_50 ; 517 ; 0 ; 0 ; 0 ;; CLOCK_50 ; CLOCK_50 ; 978 ; 0 ; 0 ; 0 ;; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50 ; 3338 ; 3 ; 0 ; 0 ;; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set ; CLOCK_50 ; 9 ; 0 ; 0 ; 0 ;; SW[15] ; CLOCK_50 ; 117 ; 0 ; 0 ; 0 ;; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 141 ; 0 ; 0 ; 0 ;; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1 ; 1 ; 0 ; 0 ;; clk_div:clkdiv_inst|clock_25MHz ; SW[15] ; 60 ; 0 ; 0 ; 0 ;; clk_div:clkdiv_inst|clock_100Hz ; SW[15] ; 5829020 ; 0 ; 0 ; 0 ;; CLOCK_50 ; SW[15] ; 288 ; 0 ; 0 ; 0 ;; SW[15] ; SW[15] ; 5829022 ; 2 ; 0 ; 0 ;; T80se:z80_inst|MREQ_n ; SW[15] ; 754 ; 1010 ; 0 ; 0 ;; clk_div:clkdiv_inst|clock_100Hz ; T80se:z80_inst|MREQ_n ; 0 ; 0 ; 256 ; 0 ;; SW[15] ; T80se:z80_inst|MREQ_n ; 0 ; 0 ; 256 ; 0 ;+-------------------------------------------------------------+-------------------------------------------------------------+----------+----------+----------+----------+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.+----------------------------------------------------------------------------------------------------------+; Recovery Transfers ;+------------+-------------------------------------------------+----------+----------+----------+----------+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;+------------+-------------------------------------------------+----------+----------+----------+----------+; CLOCK_50 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set ; 1 ; 0 ; 0 ; 0 ;+------------+-------------------------------------------------+----------+----------+----------+----------+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.+----------------------------------------------------------------------------------------------------------+; Removal Transfers ;+------------+-------------------------------------------------+----------+----------+----------+----------+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;+------------+-------------------------------------------------+----------+----------+----------+----------+; CLOCK_50 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set ; 1 ; 0 ; 0 ; 0 ;+------------+-------------------------------------------------+----------+----------+----------+----------+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.---------------; Report TCCS ;---------------No dedicated SERDES Transmitter circuitry present in device or used in design---------------; Report RSKM ;---------------No dedicated SERDES Receiver circuitry present in device or used in design+------------------------------------------------+; Unconstrained Paths ;+---------------------------------+-------+------+; Property ; Setup ; Hold ;+---------------------------------+-------+------+; Illegal Clocks ; 0 ; 0 ;; Unconstrained Clocks ; 0 ; 0 ;; Unconstrained Input Ports ; 30 ; 30 ;; Unconstrained Input Port Paths ; 317 ; 317 ;; Unconstrained Output Ports ; 124 ; 124 ;; Unconstrained Output Port Paths ; 331 ; 331 ;+---------------------------------+-------+------++------------------------------------+; TimeQuest Timing Analyzer Messages ;+------------------------------------+Info: *******************************************************************Info: Running Quartus II 64-Bit TimeQuest Timing AnalyzerInfo: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web EditionInfo: Processing started: Fri Jun 17 12:50:52 2016Info: Command: quartus_sta z80soc -c 073DE2115dInfo: qsta_default_script.tcl version: #1Warning (20028): Parallel compilation is not licensed and has been disabledInfo (21077): Low junction temperature is 0 degrees CInfo (21077): High junction temperature is 85 degrees CWarning (335093): TimeQuest Timing Analyzer is analyzing 256 combinational loops as latches.Critical Warning (332012): Synopsys Design Constraints File file not found: '073DE2115d.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"Info (332105): Deriving ClocksInfo (332105): create_clock -period 1.000 -name SW[15] SW[15]Info (332105): create_clock -period 1.000 -name CLOCK_50 CLOCK_50Info (332105): create_clock -period 1.000 -name clk_div:clkdiv_inst|clock_25MHz clk_div:clkdiv_inst|clock_25MHzInfo (332105): create_clock -period 1.000 -name clk_div:clkdiv_inst|clock_10Khz_int clk_div:clkdiv_inst|clock_10Khz_intInfo (332105): create_clock -period 1.000 -name clk_div:clkdiv_inst|clock_100Khz_int clk_div:clkdiv_inst|clock_100Khz_intInfo (332105): create_clock -period 1.000 -name clk_div:clkdiv_inst|clock_1Mhz_int clk_div:clkdiv_inst|clock_1Mhz_intInfo (332105): create_clock -period 1.000 -name clk_div:clkdiv_inst|clock_25Mhz_int clk_div:clkdiv_inst|clock_25Mhz_intInfo (332105): create_clock -period 1.000 -name clk_div:clkdiv_inst|clock_1Khz_int clk_div:clkdiv_inst|clock_1Khz_intInfo (332105): create_clock -period 1.000 -name clk_div:clkdiv_inst|clock_100Hz clk_div:clkdiv_inst|clock_100HzInfo (332105): create_clock -period 1.000 -name ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filteredInfo (332105): create_clock -period 1.000 -name ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_setInfo (332105): create_clock -period 1.000 -name T80se:z80_inst|MREQ_n T80se:z80_inst|MREQ_nInfo (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network.Info (332098): Cell: Clk_Z80 from: datab to: comboutInfo (332098): Cell: Clk_Z80 from: datad to: comboutInfo (332098): Cell: Clk_Z80~0 from: datab to: comboutInfo (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ONCritical Warning (332148): Timing requirements not metInfo (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.Info (332146): Worst-case setup slack is -18.853Info (332119): Slack End Point TNS ClockInfo (332119): ========= ============= =====================Info (332119): -18.853 -6188.176 clk_div:clkdiv_inst|clock_100HzInfo (332119): -15.271 -4622.675 SW[15]Info (332119): -9.393 -279.199 CLOCK_50Info (332119): -6.449 -1219.866 T80se:z80_inst|MREQ_nInfo (332119): -5.761 -272.854 clk_div:clkdiv_inst|clock_25MHzInfo (332119): -2.090 -36.933 ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filteredInfo (332119): -0.895 -3.964 clk_div:clkdiv_inst|clock_25Mhz_intInfo (332119): -0.665 -0.945 clk_div:clkdiv_inst|clock_1Mhz_intInfo (332119): -0.522 -0.875 clk_div:clkdiv_inst|clock_10Khz_intInfo (332119): -0.506 -0.831 clk_div:clkdiv_inst|clock_100Khz_intInfo (332119): -0.320 -0.600 clk_div:clkdiv_inst|clock_1Khz_intInfo (332146): Worst-case hold slack is -5.753Info (332119): Slack End Point TNS ClockInfo (332119): ========= ============= =====================Info (332119): -5.753 -586.538 SW[15]Info (332119): -1.638 -15.071 clk_div:clkdiv_inst|clock_100HzInfo (332119): -1.628 -63.193 T80se:z80_inst|MREQ_nInfo (332119): -0.418 -0.418 ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filteredInfo (332119): -0.319 -0.319 clk_div:clkdiv_inst|clock_1Mhz_intInfo (332119): -0.260 -0.703 CLOCK_50Info (332119): -0.127 -0.127 clk_div:clkdiv_inst|clock_10Khz_intInfo (332119): 0.048 0.000 clk_div:clkdiv_inst|clock_25MHzInfo (332119): 0.106 0.000 clk_div:clkdiv_inst|clock_100Khz_intInfo (332119): 0.440 0.000 clk_div:clkdiv_inst|clock_1Khz_intInfo (332119): 0.477 0.000 clk_div:clkdiv_inst|clock_25Mhz_intInfo (332146): Worst-case recovery slack is -2.384Info (332119): Slack End Point TNS ClockInfo (332119): ========= ============= =====================Info (332119): -2.384 -2.384 ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_setInfo (332146): Worst-case removal slack is 2.874Info (332119): Slack End Point TNS ClockInfo (332119): ========= ============= =====================Info (332119): 2.874 0.000 ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_setInfo (332146): Worst-case minimum pulse width slack is -3.000Info (332119): Slack End Point TNS ClockInfo (332119): ========= ============= =====================Info (332119): -3.000 -1318.219 SW[15]Info (332119): -3.000 -143.065 CLOCK_50Info (332119): -2.693 -619.205 clk_div:clkdiv_inst|clock_100HzInfo (332119): -2.693 -178.641 clk_div:clkdiv_inst|clock_25MHzInfo (332119): -1.285 -29.555 ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filteredInfo (332119): -1.285 -7.710 clk_div:clkdiv_inst|clock_25Mhz_intInfo (332119): -1.285 -5.140 clk_div:clkdiv_inst|clock_100Khz_intInfo (332119): -1.285 -5.140 clk_div:clkdiv_inst|clock_10Khz_intInfo (332119): -1.285 -5.140 clk_div:clkdiv_inst|clock_1Khz_intInfo (332119): -1.285 -5.140 clk_div:clkdiv_inst|clock_1Mhz_intInfo (332119): -1.285 -1.285 ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_setInfo (332119): 0.261 0.000 T80se:z80_inst|MREQ_nInfo (332102): Design is not fully constrained for setup requirementsInfo (332102): Design is not fully constrained for hold requirementsInfo: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warningsInfo: Peak virtual memory: 527 megabytesInfo: Processing ended: Fri Jun 17 12:51:07 2016Info: Elapsed time: 00:00:15Info: Total CPU time (on all processors): 00:00:12