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[/] [zap/] [trunk/] [src/] [scripts/] [Config.cfg_template] - Rev 41

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#// -----------------------------------------------------------------------------
#// --                                                                         --
#// --                   (C) 2016-2018 Revanth Kamaraj.                        --
#// --                                                                         -- 
#// -- --------------------------------------------------------------------------
#// --                                                                         --
#// -- This program is free software; you can redistribute it and/or           --
#// -- modify it under the terms of the GNU General Public License             --
#// -- as published by the Free Software Foundation; either version 2          --
#// -- of the License, or (at your option) any later version.                  --
#// --                                                                         --
#// -- This program is distributed in the hope that it will be useful,         --
#// -- but WITHOUT ANY WARRANTY; without even the implied warranty of          --
#// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the           --
#// -- GNU General Public License for more details.                            --
#// --                                                                         --
#// -- You should have received a copy of the GNU General Public License       --
#// -- along with this program; if not, write to the Free Software             --
#// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA           --
#// -- 02110-1301, USA.                                                        --
#// --                                                                         --
#// -----------------------------------------------------------------------------


# Basic template for use in other TCs.

%Config = ( 
        # CPU configuration.
        DATA_CACHE_SIZE             => 4096,    # Data cache size in bytes
        CODE_CACHE_SIZE             => 4096,    # Instruction cache size in bytes
        CODE_SECTION_TLB_ENTRIES    => 8,       # Instruction section TLB entries.
        CODE_SPAGE_TLB_ENTRIES      => 32,      # Instruction small page TLB entries.
        CODE_LPAGE_TLB_ENTRIES      => 16,      # Instruction large page TLB entries.
        DATA_SECTION_TLB_ENTRIES    => 8,       # Data section TLB entries.
        DATA_SPAGE_TLB_ENTRIES      => 32,      # Data small page TLB entries.
        DATA_LPAGE_TLB_ENTRIES      => 16,      # Data large page TLB entries.
        BP_DEPTH                    => 1024,    # Branch predictor depth.
        INSTR_FIFO_DEPTH            => 4,       # Instruction buffer depth.
        STORE_BUFFER_DEPTH          => 8,       # Store buffer depth.
        SYNTHESIS                   => 1,       # Make this to 1 to simulate compile from a synthesis perspective.

        # Testbench configuration.
        UART_TX_TERMINAL            => 1,       # 1 Enables UART TX terminal. 0 disables it.
        EXT_RAM_SIZE                => 32768,   # External RAM size.
        SEED                        => -1,      # Seed. Use -1 to use random seed.
        DUMP_START                  => 2000,    # Starting memory address from which to dump.
        DUMP_SIZE                   => 200,     # Length of dump in bytes.
        MAX_CLOCK_CYCLES            => 100000,  # Clock cycles to run the simulation for.
        ALLOW_STALLS                => 1,       # Make this 1 to allow external RAM to signal a stall.
        DEFINE_TLB_DEBUG            => 0,       # Make this 1 to define TLB_DEBUG. Useful for debugging the TLB.
        REG_CHECK                   => {"r1" => "32'h4", 
                                        "r2" => "32'd3"},      # Make this an anonymous has with entries like "r10" => "32'h0" etc.
        FINAL_CHECK                 => {"32'h100" => "32'd4", 
                                        "32'h66" => "32'h4"}       # Make this an anonymous hash with entries like verilog_address => verilog_value etc.
);

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