OpenCores
URL https://opencores.org/ocsvn/zap/zap/trunk

Subversion Repositories zap

[/] [zap/] [trunk/] [src/] [ts/] [uart/] [Config.cfg] - Rev 43

Compare with Previous | Blame | View Log

# TC config.

%Config = ( 
        # CPU configuration.
        DATA_CACHE_SIZE             => 4096,    # Data cache size in bytes
        CODE_CACHE_SIZE             => 4096,    # Instruction cache size in bytes
        CODE_SECTION_TLB_ENTRIES    => 8,       # Instruction section TLB entries.
        CODE_SPAGE_TLB_ENTRIES      => 32,      # Instruction small page TLB entries.
        CODE_LPAGE_TLB_ENTRIES      => 16,      # Instruction large page TLB entries.
        DATA_SECTION_TLB_ENTRIES    => 8,       # Data section TLB entries.
        DATA_SPAGE_TLB_ENTRIES      => 32,      # Data small page TLB entries.
        DATA_LPAGE_TLB_ENTRIES      => 16,      # Data large page TLB entries.
        BP_DEPTH                    => 1024,    # Branch predictor depth.
        INSTR_FIFO_DEPTH            => 4,       # Instruction buffer depth.
        STORE_BUFFER_DEPTH          => 16,      # Store buffer depth.
        SYNTHESIS                   => 0,       # 0 allows debug messages.

        # Testbench configuration.
        WAVES                       => 1,       # Generate waveform.
        UART0_TX_TERMINAL           => 1,       # Show TX terminal.
        UART0_RX_TERMINAL           => 1,       # Show RX terminal.
        EXT_RAM_SIZE                => 32768,   # External RAM size.
        SEED                        => -1,      # Seed. Use -1 to use random seed.
        DUMP_START                  => 2000,    # Starting memory address from which to dump.
        DUMP_SIZE                   => 200,     # Length of dump in bytes.
        MAX_CLOCK_CYCLES            => 0,       # Clock cycles to run the simulation for. 0 is forever.
        REG_CHECK                   => {},      # No registers to check.
        FINAL_CHECK                 => {}       # No memory locations to check.
);

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.