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URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

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[/] [zipcpu/] [trunk/] [bench/] [formal/] [idecode.gtkw] - Rev 209

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[*]
[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
[*] Sun Dec  2 03:08:39 2018
[*]
[dumpfile] "(null)"
[savefile] "/home/dan/bizcopy/zipcpu/bench/formal/idecode.gtkw"
[timestart] 0
[size] 1665 600
[pos] -1 -1
*-3.760617 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[sst_width] 270
[signals_width] 230
[sst_expanded] 1
[sst_vpaned_height] 143
@28
idecode.i_ce
idecode.i_clk
idecode.i_gie
idecode.i_pf_valid
idecode.i_illegal
@22
idecode.i_instruction[31:0]
idecode.i_pc[25:0]
@28
idecode.i_reset
idecode.i_stalled
@22
idecode.iword[30:0]
@200
-
@29
idecode.o_valid
@22
idecode.o_dcdA[6:0]
idecode.o_dcdB[6:0]
@28
idecode.o_ALU
idecode.o_DV
idecode.o_FP
@22
idecode.o_I[31:0]
@28
idecode.o_M
@22
idecode.o_branch_pc[25:0]
@28
idecode.o_break
@22
idecode.o_cond[3:0]
@28
idecode.o_early_branch
idecode.o_early_branch_stb
idecode.o_illegal
idecode.o_ljmp
idecode.o_lock
@22
idecode.o_op[3:0]
idecode.o_pc[25:0]
@28
idecode.o_phase
idecode.o_pipe
@22
idecode.o_preA[4:0]
idecode.o_preB[4:0]
@28
idecode.o_rA
idecode.o_rB
idecode.o_sim
@22
idecode.o_sim_immv[22:0]
@28
idecode.o_wF
idecode.o_wR
idecode.o_zI
@22
idecode.f_hidden_state[31:0]
idecode.f_insn_word[31:0]
@28
idecode.f_last_insn
idecode.f_new_insn
idecode.f_past_valid
@22
idecode.f_result[127:0]
idecode.f_this_pipe_I[20:0]
@28
idecode.fc_ALU
idecode.fc_DV
idecode.fc_FP
@22
idecode.fc_I[31:0]
@28
idecode.fc_M
idecode.fc_break
@22
idecode.fc_cond[3:0]
idecode.fc_dcdA[6:0]
idecode.fc_dcdB[6:0]
idecode.fc_dcdR[6:0]
@28
idecode.fc_illegal
idecode.fc_lock
@22
idecode.fc_op[3:0]
@28
idecode.fc_rA
idecode.fc_rB
idecode.fc_sim
@22
idecode.fc_sim_immv[22:0]
@28
idecode.fc_wF
idecode.fc_wR
idecode.pf_valid
@22
idecode.possibly_unused[5:0]
idecode.r_I[22:0]
@28
idecode.r_valid
idecode.w_ALU
@22
idecode.w_I[22:0]
@28
idecode.w_Iz
idecode.w_add
idecode.w_break
idecode.w_brev
@22
idecode.w_cis_op[4:0]
@28
idecode.w_cmptst
@22
idecode.w_cond[3:0]
idecode.w_dcdA[4:0]
@28
idecode.w_dcdA_cc
idecode.w_dcdA_pc
@22
idecode.w_dcdB[4:0]
@28
idecode.w_dcdB_cc
idecode.w_dcdB_pc
@22
idecode.w_dcdR[4:0]
@28
idecode.w_dcdR_cc
idecode.w_dcdR_pc
idecode.w_div
idecode.w_fpu
@22
idecode.w_fullI[22:0]
@28
idecode.w_ldi
idecode.w_ldilo
idecode.w_ljmp
idecode.w_ljmp_dly
idecode.w_lock
idecode.w_mem
idecode.w_mov
idecode.w_mpy
idecode.w_noop
@22
idecode.w_op[4:0]
@28
idecode.w_rA
idecode.w_rB
idecode.w_sim
idecode.w_special
idecode.w_sto
idecode.w_wF
idecode.w_wR
idecode.w_wR_n
[pattern_trace] 1
[pattern_trace] 0

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