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[/] [zipcpu/] [trunk/] [bench/] [formal/] [mcve.v] - Rev 209
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module mcve(i_clk, o_val); input wire i_clk; output reg o_val; parameter [0:0] THE_TEST = 1'b0; generate if (THE_TEST) begin always @(*) o_val = 1'b1; always @(*) assert(o_val); end else begin always @(*) o_val = 1'b0; end endgenerate endmodule