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https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
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[/] [zipcpu/] [trunk/] [rtl/] [core/] [memops.v] - Rev 2
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module memops(i_clk, i_rst, i_stb, i_op, i_addr, i_data, i_oreg, o_busy, o_valid, o_wreg, o_result, o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, i_wb_ack, i_wb_stall, i_wb_data); input i_clk, i_rst; input i_stb; // CPU interface input i_op; input [31:0] i_addr; input [31:0] i_data; input [4:0] i_oreg; // CPU outputs output wire o_busy; output reg o_valid; output reg [4:0] o_wreg; output reg [31:0] o_result; // Wishbone outputs output reg o_wb_cyc, o_wb_stb, o_wb_we; output reg [31:0] o_wb_addr, o_wb_data; // Wishbone inputs input i_wb_ack, i_wb_stall; input [31:0] i_wb_data; always @(posedge i_clk) if (i_rst) o_wb_cyc <= 1'b0; else if (o_wb_cyc) begin o_wb_stb <= (o_wb_stb)&&(i_wb_stall); o_wb_cyc <= (~i_wb_ack); end else if (i_stb) // New memory operation begin // Grab the wishbone o_wb_cyc <= 1'b1; o_wb_stb <= 1'b1; o_wb_we <= i_op; o_wb_data <= i_data; o_wb_addr <= i_addr; end initial o_valid = 1'b0; always @(posedge i_clk) o_valid <= (o_wb_cyc)&&(i_wb_ack)&&(~o_wb_we)&&(~i_rst); assign o_busy = o_wb_cyc; always @(posedge i_clk) if ((i_stb)&&(~o_wb_cyc)) o_wreg <= i_oreg; always @(posedge i_clk) if ((o_wb_cyc)&&(i_wb_ack)) o_result <= i_wb_data; endmodule
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