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[/] [zipcpu/] [trunk/] [sw/] [lib/] [mpy32u.S] - Rev 45

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mpy32u: ; unsigned R0 * unsigned R1 -> unsigned R0:R1
        PUSH    R2
        PUSH    R3
        PUSH    R4
        MOV     R0,R2
        MULU    R1,R2   ; R2 = Low order bits, low(R0) * low(R1)
        MOV     R0,R3
        LSR     16,R3   ; Put high order bits in lower half of R3
        MULU    R1,R3   ; R3 = Mid order bits, high(R0) * low(R1)
        LSR     16,R1   ; R1 = High order bits of R1, being done w/ low order
        MOV     R1,R4   ; 
        MUL     R0,R4   ; R4 = Mid order bits, low(R0) * high(R1)
        LSR     16,R0
        MULU    R1,R0   ; R0 = High order bits, high(R0) * high(R1)
        ADD     R3,R4   ; R4 = sum of mid order bits
        ADD.C   0x010000,R0     ; Add in the carry (if it happened)
        MOV     R4,R3   
        LSR     16,R3
        ADD     R3,R0   ; R0 = high order bits plus high order mid-bits 
        LSL     16,R4
        ADD     R4,R2   ; R2 = low order bits plus low order mid-bits
        ADD.C   1,R0    ; Add in the carry to R0 (if it happened)
        MOV     R2,R1   ; Place low order bits into R1
        POP     R4
        POP     R3
        POP     R2
        RET

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