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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    11:10:16 04/04/2012 
// Design Name: 
// Module Name:    rgbdtoa 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module rgbdtoa(
    input clk,	// 56MHz (or more) clock
	 input reset, 
    input select, // 0=ULA, 1=ULA+
    input ri, //
    input gi, // digital IRGB
    input bi, // inputs from standar ULA
    input hi, //
    input [7:0] rgbulap, // 8-bit input from ULA+
    output r, //
    output g, // sigma-delta encoded analog RGB signals
    output b  //
    );
 
	 reg [2:0] dacr;
	 reg [2:0] dacg;
	 reg [2:0] dacb;
 
	 always @(*) begin
		if (!select) begin
			case ({hi,ri})
				2'b00 : dacr = 3'b000;
				2'b01 : dacr = 3'b101;
				2'b10 : dacr = 3'b000;
				2'b11 : dacr = 3'b111;
			endcase
		end
		else
			dacr = rgbulap[4:2];
	end
 
	 always @(*) begin
		if (!select) begin
			case ({hi,gi})
				2'b00 : dacg = 3'b000;
				2'b01 : dacg = 3'b101;
				2'b10 : dacg = 3'b000;
				2'b11 : dacg = 3'b111;
			endcase
		end
		else
			dacg = rgbulap[7:5];
	end
 
	 always @(*) begin
		if (!select) begin
			case ({hi,bi})
				2'b00 : dacb = 3'b000;
				2'b01 : dacb = 3'b101;
				2'b10 : dacb = 3'b000;
				2'b11 : dacb = 3'b111;
			endcase
		end
		else
			dacb = {rgbulap[1:0],rgbulap[1]};
	end
 
	dac3bit dtoarojo (
		.DACout(r), 
		.DACin(dacr), 
		.Clk(clk), 
		.Reset(reset)
	);
 
	dac3bit dtoaverde (
		.DACout(g), 
		.DACin(dacg), 
		.Clk(clk), 
		.Reset(reset)
	);
 
	dac3bit dtoaazul (
		.DACout(b), 
		.DACin(dacb), 
		.Clk(clk), 
		.Reset(reset)
	);
 
endmodule
 
`define MSBI 2 // Most significant Bit of DAC input
//This is a Delta-Sigma Digital to Analog Converter
module dac3bit (DACout, DACin, Clk, Reset);
	output DACout; // This is the average output that feeds low pass filter
	input [`MSBI:0] DACin; // DAC input (excess 2**MSBI)
	input Clk;
	input Reset;
 
	reg DACout; // for optimum performance, ensure that this ff is in IOB
	reg [`MSBI+2:0] DeltaAdder; // Output of Delta adder
	reg [`MSBI+2:0] SigmaAdder; // Output of Sigma adder
	reg [`MSBI+2:0] SigmaLatch; // Latches output of Sigma adder
	reg [`MSBI+2:0] DeltaB; // B input of Delta adder
 
	always @(SigmaLatch) DeltaB = {SigmaLatch[`MSBI+2], SigmaLatch[`MSBI+2]} << (`MSBI+1);
	always @(DACin or DeltaB) DeltaAdder = DACin + DeltaB;
	always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch;
	always @(posedge Clk or posedge Reset)
	begin
		if(Reset)
		begin
			SigmaLatch <= #1 1'b1 << (`MSBI+1);
			DACout <= #1 1'b0;
		end
		else
		begin
			SigmaLatch <= #1 SigmaAdder;
			DACout <= #1 SigmaLatch[`MSBI+2];
		end
	end
endmodule