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[/] [zx_ula/] [branches/] [xilinx/] [spectrum_48k_spartan3a_for_gameduino_mod_vga_timex_hicolor_ulaplus/] [spectrum48k_tld.v] - Rev 29

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:        Dept. Architecture and Computing Technology. University of Seville
// Engineer:       Miguel Angel Rodriguez Jodar. rodriguj@atc.us.es
// 
// Create Date:    19:13:39 4-Apr-2012 
// Design Name:    ZX Spectrum
// Module Name:    tld_spartan3_sp48k
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 1.00 - File Created
// Additional Comments: GPL License policies apply to the contents of this file.
//
//////////////////////////////////////////////////////////////////////////////////
module tld_spartan3a_sp48k (
    input clk25,
	 input reset,
    output r,
    output g,
    output b,
//    output i,
    output csync,
	// ULA I/O 
	 input ear,
	 output audio_out,
	// PS/2 keyboard
	 input clkps2,
	 input dataps2,
	// SRAM memory
  	 output [17:0] sa, 
	 inout [7:0] sd1,
//	 output sramce1,
//	 output sramub1,
//	 output sramlb1,
	 output sramoe,
	 output sramwe	
    );
 
	// CPU signals
	wire [15:0] a;
	wire [7:0] cpudout;
	wire [7:0] cpudin;
	wire clkcpu;
	wire mreq_n;
	wire iorq_n;
	wire wr_n;
	wire rd_n;
	wire rfsh_n;
	wire int_n;
	wire m1_n;
 
	// VRAM signals
	wire [13:0] va;
	wire [7:0] vramdin;
	wire [7:0] vramdout;
	wire vramoe;
	wire vramcs;
	wire vramwe;
 
	// I/O
	wire mic;
	wire spk;
	wire [4:0] kbd_columns;
 
	// ULA data bus
	wire [7:0] uladout;
	wire [7:0] uladin;
 
	// SRAM data bus
	wire [7:0] sramdout;
	wire [7:0] sramdin;	
 
	// ROM data bus
	wire [7:0] romdout;
 
	wire sram_cs = a[15] & !mreq_n;
	wire ula_cs = !a[0] & !iorq_n & m1_n;
	wire vram_cs = !a[15] & a[14] & !mreq_n;
	wire port255_cs = !iorq_n && m1_n && a[7:0]==8'hFF && !rd_n;
	wire ulaplusaddr_cs = !iorq_n & m1_n & a[0] & !a[2] & a[7:6]==2'b00 & (a[15:14]==2'b10); // port BF3Bh
	wire ulaplusdata_cs = !iorq_n & m1_n & a[0] & !a[2] & a[7:6]==2'b00 & (a[15:14]==2'b11);  // port FF3Bh
	wire rom_cs = !a[15] & !a[14] & !mreq_n & !rd_n;
 
	/////////////////////////////////////
	// Clock generation
	/////////////////////////////////////
	wire clk56mhz;
   master_clock clock56mhz (
    .CLKIN_IN(clk25), 
    .CLKFX_OUT(clk56mhz), 
    .CLKIN_IBUFG_OUT(), 
    .CLK0_OUT()
    );
	reg [1:0] cnt56;
	always @(posedge clk56mhz) begin
		cnt56 = cnt56 + 1;
	end
	wire clk28 = cnt56[0];
	wire clk14 = cnt56[1];
	wire clkula = clk14;
	wire clkdacvideo = clk56mhz;
	wire clkmem = clk28;
	wire clkdacaudio = clk14;
	wire clkkbd = clk14;
 
   /////////////////////////////////////
   // ROM
   /////////////////////////////////////	
	rom the_rom (
		.clka(clkmem),
		.ena(rom_cs),
		.addra(a[13:0]),
		.douta(romdout)
	);
 
   /////////////////////////////////////
   // VRAM and upper RAM banks
   /////////////////////////////////////	
   ram_controller vram_and_upper_ram (
		.clk(clkmem),
		// Bank 1 (VRAM)
		.a1({2'b00,va}),
		.cs1_n(!vramcs),
		.oe1_n(!vramoe),
		.we1_n(!vramwe),
		.din1(vramdin),
		.dout1(vramdout),
		// Bank 2 (upper RAM)
		.a2({1'b0,a[14:0]}),
		.cs2_n(!sram_cs),
		.oe2_n(rd_n),
		.we2_n(wr_n),
		.din2(sramdin),
		.dout2(sramdout),
		// Outputs to actual SRAM on board
		.sa(sa),
		.sd(sd1),
//		.sramce(sramce1),
//		.sramub(sramub1),
//		.sramlb(sramlb1),
		.sramoe(sramoe),
		.sramwe(sramwe)
	);
 
   /////////////////////////////////////
   // The ULA
   /////////////////////////////////////	
	wire ula_r,ula_g,ula_b,ula_i,ulaplus_enabled;
	wire [7:0] rgbulaplus;
	ula the_ula (
		.clk14(clkula), 
		.reset(reset),
		.a(a), 
		.din(uladin), 
		.dout(uladout), 
		.mreq_n(mreq_n), 
		.iorq_n(iorq_n), 
		.rd_n(rd_n), 
		.wr_n(wr_n), 
		.rfsh_n(rfsh_n),
		.clkcpu(clkcpu), 
		.msk_int_n(int_n), 
		.va(va), 
		.vramdout(vramdout), 
		.vramdin(vramdin), 
		.vramoe(vramoe), 
		.vramcs(vramcs), 
		.vramwe(vramwe), 
		.ear(ear), 
		.mic(mic), 
		.spk(spk), 
		.kbrows(), 
		.kbcolumns(kbd_columns), 
		.r(ula_r), 
		.g(ula_g), 
		.b(ula_b), 
		.i(ula_i),
		.rgbulaplus(rgbulaplus),
		.ulaplus_enabled(ulaplus_enabled),
		.csync(csync)
	);
 
   /////////////////////////////////////
   // ULA/ULA+ video selector and enconding
   /////////////////////////////////////	
//	assign i = 1;
   rgbdtoa video_final_stage (
		.clk(clkdacvideo),
		.reset(reset),
		.select(ulaplus_enabled),
		.ri(ula_r),
		.gi(ula_g),
		.bi(ula_b),
		.hi(ula_i),
		.rgbulap(rgbulaplus),
		.r(r),
		.g(g),
		.b(b)
    );
 
   /////////////////////////////////////
   // The CPU Z80A
   /////////////////////////////////////	
   tv80n_wrapper cpu (
		// Outputs
		.m1_n(m1_n),
		.mreq_n(mreq_n),
		.iorq_n(iorq_n),
		.rd_n(rd_n),
		.wr_n(wr_n),
		.rfsh_n(rfsh_n),
		.halt_n(),
		.busak_n(),
		.A(a),
		.dout(cpudout), 
		// Inputs
		.reset_n(!reset),
		.clk(clkcpu),
		.wait_n(1'b1),
		.int_n(int_n),
		.nmi_n(1'b1),
		.busrq_n(1'b1),
		.di(cpudin)
   );
 
   /////////////////////////////////////
   // CPU data bus
   /////////////////////////////////////	
	assign sramdin = cpudout;
	assign uladin = cpudout;
	assign cpudin = (rom_cs)? romdout :
	                (ula_cs | vram_cs | port255_cs | ulaplusaddr_cs | ulaplusdata_cs)? uladout :
						 (sram_cs)? sramdout :
						            8'hFF;
 
   /////////////////////////////////////
   // Audio mixer
   /////////////////////////////////////	
	mixer audio_mix (
		.clkdac(clkdacaudio),
		.reset(reset),
		.ear(ear),
		.mic(mic),
		.spk(spk),
		.audio(audio_out)
	);
 
   /////////////////////////////////////
   // PS2 Keyboard
   /////////////////////////////////////	
//	wire [7:0] kbdscancode;
 
//	ps2kbd keyboard (
//		.clk(clkkbd),
//		.reset(reset),
//		.clkps2(clkps2),
//		.dataps2(dataps2),
//		.ledextended(ledextended),
//		.ledreleased(ledreleased),
//		.ledmayus(ledshift),
//		.scancode(kbdscancode),
//		.semifila(a[15:8]),
//		.columna(kbd_columns)
//	);
 
	/////////////////////////////////////
   // PS2 Keyboard
   /////////////////////////////////////	
	wire [7:0] kbdscancode;
 
	ps2keyboard keyboard (
		.CLK(clkkbd),
		.nRESET(!reset),
		.PS2_CLK(clkps2),
		.PS2_DATA(dataps2),
		.A(a[15:0]),
		.KEYB(kbd_columns)
    );
 
endmodule
 

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