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[/] [mod_sim_exp/] [trunk/] [rtl/] - Rev 95

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Last modification

  • Rev 95 2013-07-16 13:25:35 GMT
  • Author: JonasDC
  • Log message:
    new control logic for the core, allow for greater frequencies for the multiplier.
    changes:
    - autorun_cntrl: the bit selection for the exponents is now implemented with a shift register in stead of a mux. credits to Geoffrey Ottoy for new design structure.
    - mont_cntrl: gave the databus from and to the RAM more time to settle. data now has 3 clocks to get to its destination.
Path Last modification Log RSS feed
[FOLDER] mod_sim_exp/ 95  4176d 05h JonasDC View Log RSS feed
[NODE][FOLDER] branches/ 68  4308d 05h JonasDC View Log RSS feed
[NODE][FOLDER] tags/ 93  4191d 06h JonasDC View Log RSS feed
[NODE][FOLDER] trunk/ 95  4176d 05h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] bench/ 94  4189d 01h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] doc/ 92  4191d 06h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 95  4176d 05h JonasDC View Log RSS feed
[NODE][NODE][NODE][FOLDER] verilog/ 94  4189d 01h JonasDC View Log RSS feed
[NODE][NODE][NODE][FOLDER] vhdl/ 95  4176d 05h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] sim/ 94  4189d 01h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] sw/ 29  4427d 22h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] syn/ 94  4189d 01h JonasDC View Log RSS feed

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