OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [rc-1.0/] - Rev 27

Rev

Go to most recent revision | Changes | View Log | RSS feed

Last modification

  • Rev 27 2010-04-20 14:14:15 GMT
  • Author: rfajardo
  • Log message:
    Simulation library fpga_memory_primitives.v had an issue with its lpm_ram_dq module, which did not output its data.

    The data was being output to doq instead of q, the declared output. doq was also not defined anywhere else.

    Icarus Verilog did not detect this, because Verilog-2001 allows internal wires to be used without being defined. To detect this errors, one can define "`default_nettype none". After doing this, Icarus Verilog detected that error and nothing else.

    doq changed to q, error corrected.
Path Last modification Log RSS feed
[FOLDER] minsoc/ 27  5092d 01h rfajardo View Log RSS feed
[NODE][FOLDER] branches/ 1  5306d 05h root View Log RSS feed
[NODE][FOLDER] tags/ 1  5306d 05h root View Log RSS feed
[NODE][FOLDER] trunk/ 27  5092d 01h rfajardo View Log RSS feed

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.