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Last modification

  • Rev 104 2011-10-19 10:31:39 GMT
  • Author: rfajardo
  • Log message:
    Enabling modelsim simulation for current project definition.
    vhdl and verilog projects have to be separated:
    -prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS.
    -Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently.
    -prj/scripts/ splitted in:
    (they generate the input files in the right format for simulation tools)
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